Wafer Distortion Correction via Backside Layer Stress
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Solution Overview
Problem
Semiconductor wafers often exhibit global and local distortions due to out-of-plane and in-plane stresses, leading to alignment issues and overlay errors in photolithography, which affect the yield and cost of semiconductor manufacturing.
Innovation Solution
A system that determines localized distortions on semiconductor wafers using shape data and estimates the forces causing these distortions, generating a correction pattern for a backside layer to ameliorate both global and local distortions, comprising a wafer-shape meter, subject-wafer simulator, stress estimator, backside-pattern generator, and backside-pattern applier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a semiconductor wafer is used in manufacturing processes, then the wafer can be processed through deposition, lithography, etching, and other steps, but the wafer exhibits global and local distortions due to out-of-plane and in-plane stresses, leading to alignment issues and overlay errors
Solution Approach 1:
The system performs preliminary measurement of wafer shape using a wafer-shape meter before the manufacturing process, determines localized distortions and estimating forces causing these distortions, and generates a correction pattern for a backside layer that is applied in advance to ameliorate both global and local distortions, thereby preventing alignment issues and overlay errors before they occur
Solution Approach 2:
The system introduces a backside layer as an intermediary element that is applied to the backside of the wafer. This backside layer acts as a mediator to counteract the out-of-plane and in-plane stresses causing distortion, thereby improving the flatness and alignment accuracy of the wafer during subsequent manufacturing processes
2Manufacturing precision
If the wafer is not flat but bowed, then the wafer can still be processed, but layers on the bowed wafer are likewise not flat, causing misalignment and overlay errors
Solution Approach 1:
The system changes the physical parameters of the wafer by applying a backside layer that modifies the stress distribution and structural properties of the wafer. This parameter change transforms the bowed shape into a flatter configuration, thereby improving overlay accuracy without requiring the wafer to be perfectly flat from the outset
3Manufacturing precision
If correction patterns are applied to the backside of the wafer, then global and local distortions are ameliorated, but additional manufacturing steps and process complexity are introduced
Solution Approach 1:
The system extracts the distortion correction function from the main manufacturing process by applying a dedicated backside layer specifically targeted at correcting out-of-plane and in-plane distortions. This separation allows the correction step to be performed independently and systematically, reducing overall process complexity while maintaining high manufacturing precision
Data Source
AI summary
Disclosed herein is a technology related to the amelioration (e.g., correction) of global wafer distortion based on a determination of localized distortions of a semiconductor wafer. Herein, a distortion is either an out-of-plane distortion (OPD) or in-plane distortion (IPD). The reference plane for this distortion is based on the plane shared by the surface of a presumptively flat semiconductor wafer. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.