Wafer Edge Dielectric Capping for Metal Arcing Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The edge trimming process in multi-dimensional integrated chip fabrication leaves metal residue on the wafer, which can lead to arcing during high-power processes, damaging the chips and reducing yield.
Innovation Solution
A dielectric capping structure is applied to cover areas with metal residue, specifically formed only on the wafer edge in some embodiments, to prevent arcing and improve yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If edge trimming process is performed to remove parts of the wafer, then manufacturing precision is improved, but metal residue is generated on the wafer
Solution Approach 1:
A dielectric capping structure is introduced as an intermediary material between the metal residue and the plasma environment. This capping structure prevents direct interaction between the harmful plasma and the metal residue, thereby eliminating the arcing problem while preserving the benefits of the edge trimming process
2Productivity
If high-power processes are applied to fabricate integrated chips, then productivity is improved, but arcing occurs damaging the chips
Solution Approach 1:
The dielectric capping structure is formed in advance before the high-power plasma processes. This preliminary protective layer prevents arcing from occurring during subsequent high-power fabrication steps, allowing productivity to be maintained without compromising chip integrity
3Reliability
If dielectric capping structure is formed on the entire wafer, then arcing protection is improved, but manufacturing complexity increases
Solution Approach 1:
Instead of applying the dielectric capping structure uniformly across the entire wafer, the method selectively forms the capping structure only in peripheral regions where metal residue is present. This localized approach provides necessary arcing protection while minimizing additional manufacturing complexity
Data Source
AI summary
The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.