Wafer-Edge Barrier Structure for Overhanging Surface Mount Components
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Solution Overview
Problem
Current semiconductor wafer level packaging technologies face challenges in efficiently integrating and testing 3D packaging and 3DIC devices, particularly in ensuring reliable connections and preventing underfill bleeding at the wafer edge during the assembly process.
Innovation Solution
The method involves using a debond layer on a carrier for semiconductor dies, followed by insulating encapsulation, redistribution structure formation, and a first barrier structure to prevent underfill bleeding, with conductive and dielectric layers ensuring electrical connectivity and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If surface mount components are disposed on the semiconductor wafer at the wafer level, then integration efficiency and productivity are improved, but underfill bleeding at the wafer edge occurs during assembly
Solution Approach 1:
A barrier structure is introduced as an intermediary element between the underfill material and the wafer periphery. This barrier structure prevents underfill from reaching and bleeding at the wafer edge while allowing the underfill to properly fill the gaps between components. The barrier structure acts as a mediator that resolves the conflict between maintaining wafer-level integration efficiency and preventing underfill bleeding.
Solution Approach 2:
The barrier structure is disposed on the wafer before the underfill application step. By having the barrier structure in place beforehand, the patent prevents the harmful effect of underfill bleeding before it can occur. This preliminary protective action allows the underfill to be applied without risk of it reaching the wafer periphery and causing reliability issues.
2Device complexity
If wafer level packaging is used for 3D packaging and 3DIC devices, then manufacturing complexity is reduced, but ensuring reliable electrical connections becomes more difficult
Solution Approach 1:
The patent segments the wafer into multiple functional regions including component placement areas, barrier structure regions, and underfill application zones. This segmentation allows for optimized processing in each region while maintaining overall wafer-level integration. The barrier structure itself is segmented to match the pattern of surface mount components, providing localized protection at each potential bleeding point.
Solution Approach 2:
The barrier structure is formed on the wafer before component placement and underfill application. This preliminary action ensures that when underfill is later applied, the pathway for potential bleeding is already blocked. The sequential processing steps (barrier formation → component placement → underfill application) maintain wafer-level manufacturing simplicity while ensuring connection reliability.
Data Source
AI summary
A semiconductor structure includes a semiconductor wafer, a first surface mount component, a second surface mount component and a first barrier structure. The first surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of first electrical connectors. The second surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of second electrical connectors, wherein an edge of the second surface mount component is overhanging a periphery of the semiconductor wafer. The first barrier structure is disposed on the semiconductor wafer in between the second electrical connectors and the edge of the second surface mount component, wherein a first surface of the first barrier structure is facing the second electrical connectors, and a second surface of the first barrier structure is facing away from the second electrical connectors.