Wafer Trim Edge Oxide Encapsulation for Copper Burr Stability

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Solution Overview

Problem

Conventional wafer trimming processes without edge protection lead to unstable trim edges, resulting in wafer chipping and bond integrity issues, which cause yield loss and scrap, particularly when dealing with large copper features.

Innovation Solution

Implementing a conformal silicon oxide deposition on the wafer post-trim to protect the trim edge, followed by a short polish, encapsulating copper burrs with silicon oxide to stabilize the edge and ensure a smooth surface for bonding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional wafer trimming process is used without edge protection, then the trimming operation can be performed, but the trim edges become unstable leading to wafer chipping and bond integrity issues

Engineering Contradiction:
Improvetrimming operationVSAvoidbond integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

A conformal silicon oxide layer is deposited on the wafer surface before the trimming operation to protect the edges during cutting. This preliminary protective action prevents edge instability and chipping that would otherwise occur during trimming, thereby maintaining bond integrity while enabling the trimming operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The silicon oxide layer acts as an intermediary protective layer between the trimming tool and the wafer edge. This intermediate layer absorbs the mechanical stress and prevents direct contact damage to the wafer edge, resolving the contradiction between performing trimming and maintaining edge stability for bonding.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If trim edge protection with silicon oxide deposition is implemented, then bond integrity is ensured and yield loss is reduced, but the process complexity increases

Engineering Contradiction:
Improvebond integrityVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The solution changes the physical-chemical state of the wafer surface by depositing a conformal silicon oxide layer. This parameter change (adding a protective material layer) enables bond integrity and reduces yield loss, while the added process step is offset by the simplicity of the deposition technique and the elimination of subsequent repair operations.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If conventional trimming is performed without edge protection, then the process is simple, but copper burrs are not encapsulated leading to continued edge damage

Engineering Contradiction:
Improveprocess simplicityVSAvoidcopper burrs
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The silicon oxide deposition process, while adding a step to the process, converts the harmful copper burrs into encapsulated features. The burrs that would normally cause continued edge damage are sealed within the conformal oxide layer, transforming a harmful element into a contained feature that no longer threatens edge stability.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Significantly reduces line yield loss and expands the process window for thicker bow compensation nitride, making the process more robust to larger and denser copper features, while ensuring bond integrity.

Implementation Method 1

conformal silicon oxide deposition on the wafer post-trim to protect the trim edge

Methodology Applied
Scientific EffectChemical Vapor Deposition: Chemical Vapour Deposition

Implementation Method 2

followed by a short polish, encapsulating copper burrs with silicon oxide to stabilize the edge and ensure a smooth surface for bonding

Methodology Applied
Scientific EffectMechanical Polishing: Abrasion

Data Source

PatentUS20250218888A1Wafer trim edge protection
Publication Date: 2025.07.03 INTEL CORP
  • US20250218888A1 patent drawing
  • US20250218888A1 patent drawing
  • US20250218888A1 patent drawing

AI summary

Wafer trim edge protection is described. In an example, an integrated circuit structure includes a substrate having a feature including copper therein or thereon, the substrate having a recessed sidewall. A first layer including silicon and oxygen above the feature including copper. A burr including copper extending from the feature including copper and along the recessed sidewall of the substrate, along a side of the first layer including silicon and oxygen, and on a top of the first layer including silicon and oxygen. A layer including silicon and nitrogen is below or above the first layer including silicon and oxygen. A second layer including silicon and oxygen above the layer including silicon and nitrogen, wherein the second layer including silicon and oxygen encapsulates the burr including copper.