Dielectric Wafer-Edge Capping for Metal Arcing Protection
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Solution Overview
Problem
Multi-dimensional integrated chips face issues with edge trimming processes that lead to metal residue, which can cause arcing during high-power processes, damaging the chips and reducing yield due to the lack of effective countermeasures for mitigating damage from sharp edges and metal residue.
Innovation Solution
A dielectric capping structure is employed to cover areas with metal residue, specifically formed on the wafer edge or entire upper surface, using materials like silicon oxynitride, silicon nitride, or silicon dioxide to prevent arcing and improve yield by providing a protective layer during processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If edge trimming process is performed to remove parts along the perimeter, then mechanical integrity is improved, but metal residue is generated causing arcing damage
Solution Approach 1:
The patent converts the harmful metal residue left by edge trimming into a beneficial protective layer. Instead of removing all metal during edge trimming, a controlled amount is retained and then encapsulated with dielectric material, transforming the harmful residue into part of the protective capping structure that prevents arcing.
Solution Approach 2:
The patent introduces dielectric material as an intermediary substance between the metal residue and the external environment. This dielectric capping layer acts as a mediator that isolates the conductive metal residue from high-power plasma processes, preventing arcing while allowing the metal residue to remain as part of the structure.
2Device complexity
If no protective measure is taken against metal residue, then manufacturing complexity is reduced, but arcing damage occurs reducing yield
Solution Approach 1:
The patent applies preliminary action by forming the dielectric capping structure before subsequent high-power processing steps. The capping layer is deposited in advance to encapsulate metal residue, preventing arcing during later plasma etching or deposition processes, thereby protecting the wafer without requiring complex post-processing measures.
3Reliability
If dielectric capping structure is formed to cover metal residue, then arcing protection is improved, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes parameter changes in the deposition process to achieve selective capping. By controlling deposition parameters such as plasma power, gas flow, and temperature, the process automatically adjusts to deposit dielectric material preferentially in regions with metal residue while minimizing deposition in other areas, reducing the need for additional patterning steps.
Data Source
AI summary
The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.