Semiconductor Wafer Edge Layout to Suppress Corner Cracks
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Solution Overview
Problem
Existing semiconductor wafers are susceptible to cracks due to thermal shrinkage stress, particularly at the corners of semiconductor elements, which can lead to reduced withstand voltage and dielectric breakdown, especially in extreme temperature environments and mechanical stress conditions.
Innovation Solution
The semiconductor wafer design includes a configuration where the interlayer insulating film is retracted beyond the surface protective film, with specific distance and thickness relationships to prevent crack propagation, and optionally incorporates an AlSi film as a buffer to mitigate stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the interlayer insulating film is extended to cover the entire surface protective film, then the coverage area is improved, but thermal shrinkage stress concentrates at the corners of semiconductor elements causing cracks to extend to the lower side of the interlayer insulating film
Solution Approach 1:
The interlayer insulating film is selectively retracted only at the corner regions of semiconductor elements where thermal shrinkage stress concentrates, while maintaining full coverage in central areas. This localized modification reduces stress concentration at corners without sacrificing overall insulation coverage, preventing crack initiation and propagation.
Solution Approach 2:
The interlayer insulating film structure is segmented into different regions: fully extended in central areas and retracted at corner regions. This segmentation allows the film to provide adequate coverage where needed while creating stress-relief zones at corners prone to thermal shrinkage stress, thereby preventing crack extension.
2Temperature
If the distance from the end of semiconductor element to the surface protective film is reduced to minimize product thickness, then the product thickness is improved, but external stress due to thermal shrinkage stress increases causing cracks
Solution Approach 1:
The surface protective film structure is modified locally at corner regions, where the interlayer insulating film is retracted, creating a stepped configuration. This local modification provides stress relief at corners without increasing overall product thickness, maintaining compact dimensions while preventing crack initiation at high-stress zones.
3Reliability
If the interlayer insulating film is retracted at corners to reduce thermal shrinkage stress, then crack resistance is improved, but the coverage area and insulation effectiveness are reduced
Solution Approach 1:
The interlayer insulating film is retracted only at corner regions where thermal shrinkage stress concentrates, while maintaining full extension and insulation coverage in central areas. This selective retraction creates stress-relief zones at corners without compromising the overall insulation effectiveness of the device.
Solution Approach 2:
The interlayer insulating film is segmented into fully extended central regions and retracted corner regions. This segmentation strategy provides adequate insulation coverage where electrical isolation is critical while creating localized stress-relief zones at corners prone to thermal shrinkage, balancing insulation effectiveness with crack resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively suppresses crack extension in the interlayer insulating film, enhancing the durability of semiconductor devices and preventing dielectric breakdown, even under severe thermal and mechanical stress.
Implementation Method 1
external stress due to thermal shrinkage stress is applied to the end of the semiconductor element, so that a crack is likely to occur
Data Source
AI summary
A semiconductor wafer includes a semiconductor substrate on which an interlayer insulating film and a surface protective film are laminated on an upper surface. A plurality of semiconductor elements to be divided into small pieces by dicing along an opening formed in the surface protective film are formed on the semiconductor substrate. An end of the interlayer insulating film is retracted more than an end of the surface protective film with respect to an end of the semiconductor substrate to be formed by the dicing, and a shape of the end of the interlayer insulating film is set such that, in each of the semiconductor elements after the dicing, a distance Lx from a corner of the semiconductor substrate to be formed by the dicing to the end of the interlayer insulating film and a thickness d of the semiconductor substrate satisfy a certain condition.