Silicon Wafer Edge Defect Classification With Verified Learning

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Solution Overview

Problem

Existing technologies lack a clear method for evaluating and classifying edge defects in silicon wafers, which is crucial as defect management becomes important with miniaturized semiconductor processes.

Innovation Solution

A device and method using an image acquisition unit, data preprocessing, and a learning model with layered parameter formulas to accurately identify and classify edge defects in silicon wafers, enhancing defect management through iterative learning and verification of accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a learning model with layered parameter formulas is implemented to classify edge defects, then defect classification accuracy is improved, but device complexity increases

Engineering Contradiction:

Improvedefect classification accuracyVSAvoidsystem complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent uses image data as a copy or representation of the actual physical defects. Instead of directly analyzing physical defect characteristics, the system captures optical images that replicate defect appearances, enabling classification through image processing algorithms rather than complex physical measurement systems

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The patent replaces complex mechanical or physical defect analysis systems with a learning model-based computational approach. The layered parameter formulas and machine learning algorithms substitute for traditional mechanical measurement and classification methods, reducing physical device complexity while improving classification accuracy

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Measurement precision

If iterative learning and verification processes are used to improve defect classification accuracy, then measurement precision is improved, but loss of time increases

Engineering Contradiction:

Improvedefect attribute accuracyVSAvoidtraining and verification time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs preliminary actions by pre-training the learning model with layered parameter formulas before actual defect classification. The model is prepared in advance with learned parameters and structures, so that during actual operation, classification can be performed quickly without repeated iterative training, reducing time loss while maintaining high accuracy

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms where the learning model's output is verified against actual defect measurements. This feedback loop allows the system to learn from verification results and improve accuracy over time, while the learned model can then be deployed for rapid classification without requiring continuous iterative verification of each new defect

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS12536642B2Device for evaluating edge defects in a silicon wafer and method therof

Publication Date: 2026.01.27 SK SILTRON CO LTD

AI summary

A device for evaluating edge defects in a silicon wafer comprises an image acquiring unit configured to acquire image data of an edge region of the silicon wafer, a data preprocessing unit configured to measure an edge region of the silicon wafer using a measurement equipment when an edge defect is detected in the acquired image data to determine a defect attribute of the detected edge defect, and a processor.The processor controls to learn the acquired image data to output a defect attribute corresponding to the detected edge defect, and verifies an accuracy of the output defect attribute of the edge defect based on the determined defect attribute of the edge defect.