Silicon Wafer Edge Etching and Polishing Integration
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Solution Overview
Problem
Current edge treatment methods for silicon wafers, such as polishing and etching, are time-consuming and costly, and struggle to effectively smooth and damage-free the edges, especially when dealing with recent advancements in grinding and double-sided polishing, which increase the burden on edge treatment operations.
Innovation Solution
A method involving the use of an etchant to treat the edge of silicon wafers before significant reduction in flatness, specifically contacting the peripheral edge, front, and back surfaces with acidic or caustic etchants to remove damage and smooth the edges, followed by polishing, which reduces processing time and cost while avoiding excessive material consumption and wafer separation difficulties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional edge polishing operations are performed separately at a dedicated station, then edge smoothness is improved, but processing time and operational complexity increase
Solution Approach 1:
The patent combines edge polishing with the existing double-sided polishing operation by integrating an edge polishing surface into the polishing apparatus. This allows simultaneous polishing of both surfaces and the edge in a single continuous operation, eliminating the need for separate edge polishing stations and reducing processing time while maintaining edge smoothness quality.
Solution Approach 2:
The polishing apparatus is designed to perform multiple functions: polishing both front and back surfaces of the wafer, and simultaneously polishing the edge. This multi-functional approach consolidates what were previously separate operations into one unified process, improving efficiency without sacrificing edge quality.
2Manufacturing precision
If edge polishing is performed as a separate operation with multiple steps (removing wafers, aligning, polishing, cleaning, drying), then edge quality is improved, but device complexity and operational difficulty increase
Solution Approach 1:
The patent merges multiple discrete edge treatment steps into a single integrated polishing operation. The edge polishing surface is positioned to contact the edge during the same polishing cycle used for surfaces, eliminating separate alignment, handling, and cleaning steps that were required in conventional separate edge polishing operations.
Solution Approach 2:
The edge polishing surface is pre-positioned and configured within the polishing apparatus before wafer loading. The geometry and positioning of the edge polishing surface are designed in advance to automatically engage the edge during the polishing operation, eliminating the need for complex real-time alignment operations.
3Manufacturing precision
If recent double-sided polishing operations remove more material, then surface flatness is improved, but the burden on edge treatment operations increases
Solution Approach 1:
The patent addresses the increased burden on edge treatment caused by aggressive double-sided polishing by integrating edge polishing into the same operation. This allows the edge to be treated with the same increased efficiency and material removal capabilities, maintaining productivity while achieving the required edge quality despite higher material removal from the surfaces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method simplifies the edge treatment process, reduces processing time and costs, and achieves smooth, damage-free edges, improving wafer quality and throughput by addressing edge roughness and damage caused by prior processing steps.
Implementation Method 1
contacting with an etchant (i) the peripheral edge of the wafer, (ii) the edge portion of the front surface of the wafer, and (iii) the edge portion of the back surface of the wafer
Data Source
AI summary
The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.