Wafer Edge Protection via Flush Encapsulation and Mold Geometry
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Solution Overview
Problem
The existing methods for protecting the peripheries of semiconductor wafers during processing are inadequate, leading to edge chipping and cracking due to exposure and excessive stress, which can propagate damage and reduce yield.
Innovation Solution
A method involving a mold with an inner diameter greater than the wafer's outer diameter, where the encapsulation material covers the active surface and side surfaces but not the periphery, reducing stress and ensuring the encapsulation material is flush with the wafer's side surfaces, thereby protecting the edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a mold body with smaller inner diameter than wafer outer diameter is used to contact the wafer surface for encapsulation, then contamination is prevented by blocking mold compound from reaching the wafer edge, but the wafer periphery becomes exposed and vulnerable to edge chipping and cracking
Solution Approach 1:
The patent transitions from a 2D encapsulation approach (mold body contacting only the wafer surface) to a 3D approach where the mold body extends beyond the wafer perimeter. This dimensional extension allows the mold to simultaneously protect the wafer surface from contamination and provide mechanical support to the periphery, eliminating the trade-off between contamination prevention and edge integrity.
2Reliability
If the mold body contacts the wafer periphery during encapsulation, then edge protection is provided, but excessive stress is imposed on the wafer causing potential damage
Solution Approach 1:
The patent modifies the geometric parameters of the mold body, specifically extending its diameter beyond the wafer outer diameter and configuring it to contact the carrier substrate rather than directly pressing on the wafer periphery. This parameter change allows the mold to provide edge protection through geometric confinement while distributing stress to the more robust carrier substrate, reducing the risk of wafer damage.
3Reliability
If the mold inner diameter is made larger than the wafer outer diameter to allow full encapsulation, then edge protection and stress reduction are achieved, but the encapsulation material may not properly contain the periphery
Solution Approach 1:
The patent introduces the carrier substrate as an intermediary element between the wafer and the mold body. The mold contacts and contains the carrier substrate, which in turn supports the wafer. This intermediary approach allows the mold to provide geometric containment and edge protection without directly constraining the fragile wafer periphery, maintaining both containment precision and edge protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents edge damage and stress, maintaining the integrity of the semiconductor devices and increasing the yield by ensuring the encapsulation material is flush with the wafer's side surfaces, allowing for safer handling and processing.
Implementation Method 1
The encapsulation material may be cured, and the mold may be removed from contact with the periphery of the wafer
Data Source
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AI summary
Methods of processing semiconductor wafers may involve, for example, encapsulating an active surface and each side surface of a wafer of semiconductor material, a plurality of semiconductor devices located on the active surface of the wafer, an exposed side surface of an adhesive material located on a back side surface of the wafer, and at least a portion of a side surface of a carrier substrate secured to the wafer by the adhesive material in an encapsulation material. At least a portion of the side surface of the adhesive material may be exposed by removing at least a portion of the encapsulation material. The carrier substrate may be detached from the wafer. Processing systems and in-process semiconductor wafers are also disclosed.