Wafer Edge Inspection via Image Compression and Sinusoidal Fitting
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Solution Overview
Problem
Current wafer edge inspection and metrology systems face challenges in accurately centering wafers during edge bead removal processes, leading to defects in integrated circuit devices due to variability in material removal processes and misalignment of resist layers, which can result in uneven substrate layers and contamination.
Innovation Solution
A wafer edge inspection system that acquires and compresses images of the wafer edge to generate a composite image, using sinusoidal line fitting to locate features such as the edge bead removal line and determine characteristics like resist edge positions, enabling precise alignment and quality control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If wafer edge inspection systems use conventional imaging methods without compression, then image detail is preserved, but data processing time and computational load increase
Solution Approach 1:
The patent extracts only the essential features from full wafer images by compressing them into representative line profiles. Instead of processing entire high-resolution images, the system extracts radial intensity profiles that contain the critical edge bead and wafer feature information, significantly reducing data volume while maintaining measurement precision for edge inspection
Solution Approach 2:
The patent transforms 2D wafer edge images into 1D radial intensity profiles by integrating along angular directions. This dimensional reduction converts complex image data into simplified line profiles that preserve the essential geometric and intensity characteristics needed for edge bead detection and wafer centering, reducing computational complexity while maintaining measurement accuracy
2Manufacturing precision
If wafer centering is not precisely controlled during EBR, then processing speed is maintained, but resist layer misalignment occurs leading to substrate layer unevenness and defects
Solution Approach 1:
The patent implements a feedback control system where the inspection system measures actual wafer position and edge bead characteristics, then feeds this information back to adjust wafer centering for subsequent EBR processes. The system uses measured radial intensity profiles to determine wafer centering errors and provides corrective feedback to positioning mechanisms, ensuring precise resist layer alignment while maintaining efficient throughput through automated closed-loop control
Solution Approach 2:
The patent performs preliminary wafer inspection and centering measurement before the actual EBR process. By acquiring and analyzing wafer edge images and determining centering accuracy in advance, the system can pre-adjust wafer positioning to ensure optimal alignment for the subsequent resist removal process, preventing misalignment defects before they occur
Data Source
AI summary
Some aspects of the present invention relate to a wafer inspection method. A plurality of images is acquired about an edge portion of a wafer. Each of the images comprises a pixel array having a first dimension and a second dimension. A composite image of compressed pixel arrays is generated by compressing each of the pixel arrays in the first dimension and concatenating the pixel arrays. The composite image is analyzed to identify a wafer feature, for example using a sinusoidal line fit.