Wafer Trim Edge Oxide Encapsulation for Stable Copper Bonding

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Solution Overview

Problem

Conventional wafer trimming processes without edge protection lead to unstable trim edges, resulting in chipping and bond integrity issues, which cause significant line yield loss and scrap in semiconductor fabrication.

Innovation Solution

Implementing a conformal silicon oxide deposition on the wafer post-trim to protect the trim edge, followed by a short polish to ensure a smooth surface for bonding, and encapsulating copper burrs with silicon oxide to prevent interference with bonding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional wafer trimming processes are used without edge protection, then the trimming operation can be completed, but the trim edges become unstable resulting in chipping and bond integrity issues

Engineering Contradiction:
Improvebond integrityVSAvoidtrim edge stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

A conformal silicon oxide layer is deposited on the wafer surface before the trim operation to protect the edge during cutting. This preliminary protective action prevents chipping and maintains edge stability throughout the trimming process, directly resolving the contradiction between achieving clean trim edges and maintaining bond integrity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The silicon oxide layer acts as a cushioning protective barrier deposited beforehand on the wafer surface. This layer absorbs and distributes stresses during trimming, preventing direct mechanical damage to the silicon edge, thereby maintaining both trim edge stability and preventing chipping that would compromise bond integrity.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If trim edge protection is implemented with conformal silicon oxide deposition, then bond integrity is improved, but additional process steps are required

Engineering Contradiction:
Improvebond integrityVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The conformal silicon oxide deposition serves multiple functions simultaneously: it protects the trim edge during cutting, provides a smooth surface for subsequent bonding operations, and acts as a stress buffer. By combining these functions into a single process step, the patent improves bond integrity while minimizing the increase in process complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If copper features are made larger and denser to increase capacity, then functional density is improved, but trim edge stability deteriorates due to copper burrs interfering with bonding

Engineering Contradiction:
Improvefunctional densityVSAvoidbonding quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The conformal silicon oxide layer acts as an intermediary barrier between the copper features and the bonding interface. It encapsulates copper burrs and prevents them from interfering with the bonding process, allowing larger and denser copper features to be used without compromising bonding quality, thereby enabling increased functional density.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The thin conformal silicon oxide film flexibly conforms to the complex three-dimensional topology of dense copper features while providing continuous protection. This thin film encapsulates copper burrs and irregularities, maintaining bonding quality even with high-density copper interconnect structures.

Inventive Principle:
Principle #30Flexible shells and thin films

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Significantly reduces line yield loss and expands the process window for thicker bow compensation nitride, making the process more robust to larger and denser copper features, while ensuring bond integrity.

Implementation Method 1

conformal silicon oxide deposition on the wafer post-trim

Methodology Applied
Scientific EffectChemical Vapor Deposition: Chemical Vapour Deposition

Implementation Method 2

followed by a short polish to ensure a smooth surface for bonding

Methodology Applied
Scientific EffectMechanical Polishing: Abrasion

Data Source

PatentEP4589635A1Wafer trim edge protection
Publication Date: 2025.07.23 INTEL CORP
  • EP4589635A1 patent drawingFigure 1A~1B
  • EP4589635A1 patent drawingFigure 2(a)~2(c)
  • EP4589635A1 patent drawingFigure 3(a)~3(c)

AI summary

Wafer trim edge protection is described. In an example, an integrated circuit structure includes a substrate having a feature including copper therein or thereon, the substrate having a recessed sidewall. A first layer including silicon and oxygen above the feature including copper. A burr including copper extending from the feature including copper and along the recessed sidewall of the substrate, along a side of the first layer including silicon and oxygen, and on a top of the first layer including silicon and oxygen. A layer including silicon and nitrogen is below or above the first layer including silicon and oxygen. A second layer including silicon and oxygen above the layer including silicon and nitrogen, wherein the second layer including silicon and oxygen encapsulates the burr including copper.