Semiconductor Wafer Edge Oxide for Residue-Free Electroless Plating

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Solution Overview

Problem

Existing semiconductor manufacturing methods face challenges in preventing the formation of adhesive residue during electroless plating, which can lead to wafer attachment issues in subsequent processing steps due to the use of protective tapes adhering to exposed silicon surfaces.

Innovation Solution

The method involves forming an oxide film on the outer peripheral region of the semiconductor wafer before electroless plating to prevent exposure of silicon, thereby reducing the adhesion of protective tape residues and minimizing wafer attachment problems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If protective tape is applied to prevent adhesive residue during electroless plating, then adhesion prevention is improved, but wafer handling complexity increases due to attachment risks

Engineering Contradiction:
Improveadhesion preventionVSAvoidwafer handling complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies protective tape to the back surface of the wafer before the electroless plating process. This preliminary action prevents adhesive residue from forming on the back surface during plating, eliminating the need for subsequent cleaning steps and reducing wafer handling complexity while maintaining reliability

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If electroless plating is performed on the outer peripheral region, then plating coverage is improved, but adhesive residue formation increases on exposed silicon surfaces

Engineering Contradiction:
Improveplating coverageVSAvoidadhesive residue formation
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent applies different treatments to different regions of the wafer: the front surface outer peripheral region receives electroless plating for improved coverage, while the back surface is covered with protective tape to prevent adhesive residue formation. This local differentiation resolves the contradiction between achieving complete plating coverage and preventing harmful adhesive residue

Inventive Principle:
Principle #3Local quality

3Productivity

If protective tape is removed after plating, then processing continuity is improved, but adhesive residue may form on exposed surfaces

Engineering Contradiction:
Improveprocessing continuityVSAvoidadhesive residue
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The protective tape is applied to the back surface before plating and remains in place throughout the plating process. This preliminary positioning ensures that when the tape is eventually removed, no adhesive residue is present on the back surface, maintaining both processing continuity and preventing harmful residue formation

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively prevents adhesive residue formation, ensuring smooth wafer handling and processing by eliminating the risk of wafer attachment to stages or conveyance arms, thereby enhancing manufacturing efficiency.

Implementation Method 1

forming an oxide film on the outer peripheral region of the semiconductor wafer before electroless plating

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS12451356B2Manufacturing method for semiconductor device
Publication Date: 2025.10.21 FUJI ELECTRIC CO LTD
  • US12451356B2 patent drawing
  • US12451356B2 patent drawing
  • US12451356B2 patent drawing

AI summary

Provided is a manufacturing method for a semiconductor device including forming a first electrode layer on a front surface of a wafer, implanting, into an outer peripheral region of the front surface of the wafer, a heavy ion of an element in third and subsequent rows of a periodic table, forming an oxide film in the outer peripheral region into which the heavy ion has been implanted, and forming a second electrode layer on the first electrode layer by plating. A dose of the heavy ion may be 1E15 cm−2 or more. A depth of an implantation range of the heavy ion into the wafer may be 0.02 μm or more. The heavy ion may be an As ion, a P ion, or an Ar ion.