Wafer Edge Partial Die for Stacked Die Yield
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Solution Overview
Problem
Conventional wafer bonding techniques face challenges in achieving flat wafer topology, leading to bubble formation and delamination issues, particularly at the wafer edge, which results in yield loss and rejection of stacked wafer assemblies.
Innovation Solution
The use of conductive bond pads formed over inductors on partial dies, connected between opposing wafers, improves wafer flatness and topography, reducing bubble formation and delamination by enhancing the wafer bonding process through a different mask set for partial dies at the wafer edge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wafer bonding techniques are used to bond stacked wafers, then wafer-level integration is achieved, but bubble formation and delamination occur at wafer edges due to non-flat topology
Solution Approach 1:
The patent applies different mask sets for different regions of the wafer: a first mask set for fully functional dies in the center region and a second mask set for partial dies at the edge region. This local differentiation optimizes pattern density and metal layer thicknesses in each region, achieving flat wafer topology at the edges while maintaining functionality in the center, thereby preventing bubble formation and delamination during bonding.
2Ease of manufacture
If the same mask set is used for all dies on the wafer, then manufacturing simplicity is maintained, but pattern density variation causes non-uniform topology and bonding defects
Solution Approach 1:
The patent implements local quality by using a first mask set for fully functional dies and a second mask set for partial dies. The second mask set is specifically designed to compensate for edge effects by adjusting pattern density and metal layer thicknesses, ensuring uniform topology across the entire wafer surface while maintaining ease of manufacture through a systematic two-mask approach.
Solution Approach 2:
The patent changes key parameters (pattern density and metal layer thicknesses) specifically for the second mask set used on partial dies. By adjusting these parameters at the wafer edges, the topology uniformity is improved without compromising the manufacturing process, as the parameter changes are localized and systematic rather than random or complex.
3Productivity
If partial dies at wafer edges are fabricated with standard patterns, then manufacturing consistency is maintained, but bubble formation occurs during bonding leading to yield loss
Solution Approach 1:
The patent applies local quality by using a specialized second mask set for partial dies at the wafer edges, which optimizes pattern density and metal layer thicknesses in this vulnerable region. This localized optimization prevents bubble formation during bonding, eliminating the harmful effect while maintaining high wafer yield through improved edge die reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces bubble formation and delamination, increasing the yield of integrated circuit devices by ensuring robust adhesion and consistent topography during wafer stacking.
Implementation Method 1
Wafer bonding can utilize dielectric to dielectric bonding, such as oxide bonding
Implementation Method 2
hybrid bonding that utilizes metals bonding to metals and dielectric bonding to dielectric
Data Source
AI summary
A stacked wafer assembly and method for fabricating the same are described herein. In one example, a stacked wafer assembly includes a first wafer bonded to a second wafer. The first wafer includes a plurality of fully functional dies and a first partial die formed thereon. The second wafer includes a plurality of fully functional dies and a first partial die formed thereon. Bond pads formed over an inductor of the first partial die of the first wafer are bonded to bond pads formed on the first partial die of the second wafer to establish electrical connection therebetween.