Semiconductor Wafer Edge Planarization for Bonding

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Solution Overview

Problem

The existing methods for manufacturing semiconductor wafers result in significant wasteful disposal of edge portions during the bonding process, leading to reduced effective chip areas and increased wastage.

Innovation Solution

The method involves forming insulators of specific thickness and structure on both the central and edge portions of the wafers to ensure uniform height, allowing for better bonding and reducing unbonded areas by using techniques like CMP and etching to planarize surfaces, thereby eliminating differences in level and enhancing chip area utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional bonding methods are used without planarization, then the bonding process is simpler and faster, but significant wasteful disposal of edge portions occurs and effective chip areas are reduced

Engineering Contradiction:

Improveeffective chip area utilizationVSAvoidbonding process complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent applies preliminary planarization actions by forming insulators of specific thickness on both central and edge portions before bonding. This pre-leveling of surfaces ensures that when bonding occurs, the entire wafer surface including edges is properly aligned, eliminating the need to discard edge portions and maximizing effective chip area utilization.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent changes the physical parameters of the wafer surfaces by controlling insulator thickness to achieve uniform height across central and edge portions. This parameter adjustment (insulator thickness control) transforms the surfaces from non-uniform to uniform, enabling complete bonding without edge disposal and resolving the contradiction between productivity and process complexity.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If edge portions are disposed of to ensure proper bonding, then bonding quality is maintained, but wasteful disposal increases and effective chip areas decrease

Engineering Contradiction:

Improvebonding qualityVSAvoidwafer material waste

Core Design Contradiction:

ReliabilityVSLoss of substance

Solution Approach 1:

The patent applies local quality by forming insulators with specific thickness characteristics on different regions (central and edge portions) of the wafer. This localized treatment ensures that each region achieves the required height for proper bonding, allowing the entire wafer including edges to be utilized without compromising bonding quality while eliminating material waste.

Inventive Principle:

Principle #3Local quality

3Manufacturing precision

If insulators of different thickness are used on central and edge portions, then bonding alignment is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improvebonding alignment precisionVSAvoidinsulator structure complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the insulator structure into different thickness regions (first insulator on central portion, second insulator on edge portion) to achieve proper bonding alignment. This segmentation allows each region to be optimized independently for its specific bonding requirements, improving alignment precision while managing structural complexity through systematic division.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces wasteful disposal of trimming portions and edge portions, increasing the effective chip areas by ensuring complete bonding between the central and edge regions, thus minimizing waste and optimizing wafer utilization.

Implementation Method 1

a first difference in level between a central portion and an edge portion of an upper surface of the first wafer, and a second difference in level between a central portion and an edge portion of an upper surface of the second wafer are eliminated by chemical mechanical polishing (CMP)

Methodology Applied

Scientific EffectChemical Mechanical Polishing:

Implementation Method 2

using techniques like CMP and etching to planarize surfaces, thereby eliminating differences in level

Methodology Applied

Scientific EffectEtching:

Data Source

PatentUS11532589B2Semiconductor wafer and method of manufacturing the same

Publication Date: 2022.12.20 KIOXIA CORP

AI summary

In one embodiment, a semiconductor wafer includes a first substrate, a first insulator provided on the first substrate, and a plurality of first pads provided in the first insulator. The wafer further includes a second insulator provided on the first insulator, a plurality of second pads provided on the first pads in the second insulator, a stacked film alternately including a plurality of first insulating layers and a plurality of second insulating layers provided in the second insulator, and a second substrate provided on the second insulator. Furthermore, the first insulator and the second insulator are connected to each other between an edge face of the first insulator and an edge face of the second insulator, and the second insulator intervenes between the first insulator and the stacked film at the edge faces of the first and second insulators.