Semiconductor Wafer Edge Planarization for Defocus Prevention
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Solution Overview
Problem
The challenge in increasing the integration density of semiconductor devices lies in the difficulty of reducing pattern linewidths, which requires advanced and costly exposure technologies, and results in issues such as defocus problems and pattern failures at the wafer edge region, leading to discarded semiconductor chips and potential particle sources in subsequent fabrication processes.
Innovation Solution
A method involving the sequential stacking of a mold layer, a supporting layer, and mask layers on a substrate, with the formation of step-difference compensation patterns and mask patterns to etch holes in the mold layer, addressing defocus issues and preventing pattern formation on the wafer edge region, thereby enhancing production yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If advanced exposure technologies are used to reduce pattern linewidths, then integration density is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
A planarization layer is formed in advance on the mold layer before performing the exposure process. This preliminary action equalizes the surface height, allowing standard exposure technologies to work effectively without requiring advanced equipment, thus resolving the contradiction between manufacturing precision and device complexity
Solution Approach 2:
The planarization layer acts as an intermediary element between the mold layer and the photoresist layer. It mediates the height difference issue, enabling the exposure process to proceed with conventional technologies while achieving the desired pattern linewidth precision
2Productivity
If exposure is performed on the wafer edge region, then chip production area is increased, but defocus problems and pattern failures occur
Solution Approach 1:
The planarization layer is selectively formed only in the wafer edge region where height differences exist, while leaving the wafer inner region unchanged. This local quality approach allows the wafer edge region to achieve proper focus for pattern formation, enabling increased chip production area without sacrificing pattern reliability
Solution Approach 2:
Instead of trying to make the entire wafer surface uniform or avoiding the wafer edge region, the invention inverts the approach by adding material specifically to the low-lying wafer edge region. This inversion allows the edge region to reach the same effective height as the inner region, enabling reliable pattern formation across the entire wafer surface
Data Source
AI summary
A method of fabricating a semiconductor device including preparing a substrate including a wafer inner region and a wafer edge region, the wafer inner region including a chip region and a scribe lane region, sequentially stacking a mold layer and a supporting layer on the substrate, forming a first mask layer on the supporting layer, the first mask layer including a first stepped region on the wafer edge region, forming a step-difference compensation pattern on the first stepped region, forming a second mask pattern including openings, on the first mask layer and the step-difference compensation pattern, and sequentially etching the first mask layer, the supporting layer, and the mold layer using the second mask pattern as an etch mask to form a plurality of holes in at least the mold layer may be provided.