Wafer Edge Protection via Double Patterning Masking
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Solution Overview
Problem
Wafer edge topography issues during oxide-oxide or copper-oxide hybrid bonding lead to voids and delamination due to Cu Edge Bead Removal and Litho Edge Bead Removal processes, which introduce discontinuities in film thickness and topography, necessitating effective edge protection techniques.
Innovation Solution
A double patterning method with edge exposure is employed, where a first mask is patterned over the entire wafer surface, and a second mask is used to block trench formation at the edge region, preventing voids and ensuring a smooth surface for wafer bonding by selectively removing copper from the edge region without creating topography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of substance
If Cu Edge Bead Removal is performed to remove copper in deep trenches at the wafer edge, then copper is removed from the edge, but large voids are created that cannot be properly filled or planarized, leading to delamination
Solution Approach 1:
A mask is formed on the wafer edge region before the Cu EBR process to prevent copper removal at the edges. This preliminary protective action ensures that copper interconnects are preserved at the wafer periphery, avoiding the formation of voids and maintaining a planar surface topology that is suitable for subsequent bonding processes
Solution Approach 2:
The solution applies different treatment to different regions of the wafer: the mask selectively protects only the edge region (typically within 1mm of the periphery) while allowing standard Cu EBR processing in the bulk areas. This localized approach maintains copper interconnects where needed for bonding while still enabling copper removal in regions where it is appropriate
2Ease of operation
If Litho Edge Bead Removal is performed to expose the wafer edge during etching, then the wafer edge is exposed, but a large discontinuity in film thickness is created at the EBR location
Solution Approach 1:
A mask is deposited and patterned on the wafer edge region prior to etching and Cu EBR processes. This preliminary masking prevents the formation of film thickness discontinuities by protecting the edge region from copper removal, thereby maintaining a uniform film profile across the wafer surface including the bonding interface
Solution Approach 2:
The mask serves as an intermediary protective layer between the etching/EBR process and the copper interconnects at the wafer edge. This intermediary structure allows the wafer edge to remain exposed for bonding access while preventing the harmful effects of copper removal and film thickness variation
3Productivity
If standard Cu EBR and Litho EBR processes are used, then copper is removed from the edge and wafer edge is exposed, but voids and topography discontinuities are created that prevent void-free bonding
Solution Approach 1:
A mask is formed on the wafer edge region before Cu EBR and etching processes to prevent copper removal at the edges. This preliminary protective action ensures that copper interconnects are preserved at the wafer periphery, avoiding the formation of voids and maintaining a planar surface topology that is suitable for subsequent bonding processes
Solution Approach 2:
The solution applies different treatment to different regions of the wafer: the mask selectively protects only the edge region (typically within 1mm of the periphery) while allowing standard Cu EBR processing in the bulk areas. This localized approach maintains copper interconnects where needed for bonding while still enabling copper removal in regions where it is appropriate
Data Source
AI summary
Wafer bonding edge protection techniques are provided. In one aspect, a method of forming Cu interconnects in a wafer includes: forming a dielectric layer on the wafer; forming a first mask on the dielectric layer; patterning the first mask with a footprint/location of the Cu interconnects, wherein the patterning of the first mask is performed over an entire surface of the wafer; forming a second mask on the first mask, wherein the second mask covers a portion of the patterned first mask at an edge region of the wafer; patterning trenches in the dielectric layer through the first mask and the second mask, wherein the second mask blocks formation of the trenches at the edge region of the wafer and thereby provides edge protection during patterning of the trenches; and forming the Cu interconnects in the trenches. A wafer bonding method and interconnect structure are also provided.