Wafer Edge Ring Grinding for Precision Singulation Alignment

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Solution Overview

Problem

Traditional singulation methods for semiconductor wafers, such as sawing, induce die chipping and cracking, which reduce yield and affect device reliability due to the thinness of semiconductor die, making precise alignment and processing challenging.

Innovation Solution

A method involving a semiconductor wafer with a metal layer covering the edge ring, where the edge ring is ground to create an edge exclusion area, and the wafer is aligned using a camera with alignment features in this area, allowing for precise alignment and singulation using techniques like sawing, lasering, or plasma etching, while minimizing damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional sawing methods are used for singulation, then the singulation process can be completed, but die chipping and cracking occur which reduce yield and reliability

Engineering Contradiction:
Improvesingulation completionVSAvoiddie integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by creating an edge exclusion area and applying a metal coating to the edge ring before the singulation process. This preparatory treatment protects the die edges from chipping and cracking during sawing, thereby maintaining die integrity while completing the singulation process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The metal coating applied to the edge ring serves as a cushioning layer that absorbs and distributes the mechanical stress during sawing. This beforehand cushioning prevents stress concentration at the die edges, reducing chipping and cracking while allowing the singulation to proceed.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Manufacturing precision

If precise alignment is achieved using camera and alignment features, then singulation accuracy improves, but the process complexity increases

Engineering Contradiction:
Improvealignment accuracyVSAvoidalignment process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The alignment features are integrated directly into the edge exclusion area structure, allowing the system to self-align during the singulation process. The camera detects these built-in features to automatically determine the correct positioning, achieving precise alignment without requiring complex external alignment equipment or procedures.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the precision and reliability of the singulation process, reducing die breakage and improving yield by allowing for accurate alignment and processing of thin semiconductor die without inducing significant chipping or cracking.

Implementation Method 1

aligning the wafer for singulation using an infrared camera. The infrared camera may use two or more alignment features in the edge exclusion area

Methodology Applied
Scientific EffectInfrared radiation detection: Infrared Radiation

Implementation Method 2

The metal coating may be applied through one of sputtering, evaporation, or plating

Methodology Applied
Scientific EffectSputtering: Sputtering

Implementation Method 3

The metal coating may be applied through one of sputtering, evaporation, or plating

Methodology Applied
Scientific EffectEvaporation: Evaporation

Implementation Method 4

creating an edge exclusion area through removal of the edge ring. Removal of the edge ring may include grinding and washing the semiconductor wafer

Methodology Applied
Scientific EffectAbrasion: Abrasion

Data Source

PatentUS11676863B2Structures for aligning a semiconductor wafer for singulation
Publication Date: 2023.06.13 SEMICON COMPONENTS IND LLC
  • US11676863B2 patent drawing
  • US11676863B2 patent drawing

AI summary

Implementations of a method for aligning a semiconductor wafer for singulation may include: providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of die and the plurality of die may be separated by streets. The semiconductor wafer may include an edge ring around a perimeter of the wafer on the second side of the wafer. The wafer may also include a metal layer on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to create an edge exclusion area and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion area on the second side of the wafer. Aligning the wafer may include using three or more alignment features included in the edge exclusion area.