Wafer-Level Encapsulation with Pillar Bumps for Thinner Packages
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Solution Overview
Problem
Current semiconductor manufacturing processes are complex and inefficient, requiring multiple steps and materials, which increases costs, time to market, and environmental impact, while also limiting the miniaturization of semiconductor devices and packages.
Innovation Solution
A single-shot encapsulation method is introduced, which forms low-profile bumps and redistribution layers on semiconductor wafers, allowing for the packaging of semiconductor die with reduced material usage and without the need for internal substrates or wire bonds, enabling the creation of thinner, more reliable semiconductor packages with improved parasitic characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional multi-step semiconductor packaging processes are used, then reliable electrical connections and structural support are achieved, but manufacturing complexity and time increase significantly
Solution Approach 1:
The patent combines multiple separate packaging operations (die attachment, wire bonding, encapsulation, and trimming) into a single integrated molding process. The mold cavity is designed to simultaneously perform all these functions, eliminating the need for sequential processing steps and reducing manufacturing complexity while maintaining product reliability.
Solution Approach 2:
The molding process is designed to serve multiple functions simultaneously: it provides structural support, creates electrical connections through integrated leads, performs encapsulation, and enables easy separation of multiple packages. This multi-functional approach replaces several specialized processes with a single universal molding operation.
2Reliability
If traditional semiconductor packaging with internal substrates and wire bonds is used, then electrical interconnection is achieved, but material consumption and environmental impact increase
Solution Approach 1:
The patent extracts and eliminates unnecessary intermediate components from the packaging structure. By removing internal substrates and wire bonds, the design directly connects the semiconductor die to the external leads through the mold compound itself, reducing material consumption and simplifying the overall structure while maintaining electrical interconnection functionality.
Solution Approach 2:
The process eliminates the need for separate trimming and wire bond removal steps by designing the mold cavity to create finished packages directly. Excess material is minimized through precise cavity design, and the process naturally produces ready-to-use packages without requiring additional material removal or recovery operations.
3Strength
If conventional packaging processes are used, then adequate structural support is provided, but package size and footprint are larger than necessary
Solution Approach 1:
The patent uses the mold compound as a thin, flexible encapsulating layer that provides adequate structural support and protection without adding excessive thickness. The mold compound conforms closely to the die and lead structure, creating a compact package with minimal footprint while maintaining necessary mechanical strength and environmental protection.
4Reliability
If multiple manufacturing steps are used, then process control and quality assurance are maintained, but production time and cost increase
Solution Approach 1:
The mold cavity is pre-designed and pre-positioned with all necessary features (leads, cavities, and alignment structures) before the die is inserted. This preliminary preparation allows the actual packaging to occur in a single rapid molding operation, eliminating the need for multiple sequential steps and significantly improving manufacturing efficiency while maintaining quality control through the precision of the pre-designed mold.
Data Source
Figure 1a~1b
Figure 1c~1e
Figure 2a~2c
AI summary
A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps (140) is formed over the semiconductor wafer. A solder (142) is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die (124) after forming the pillar bumps while the semiconductor wafer is on a temporary carrier (190). An encapsulant (186) is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.