Wafer Etching Process for Backside Cavity Formation
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Solution Overview
Problem
As semiconductor devices undergo miniaturization, the formation of backside cavities with precise etch profile angles and reduced dependency on crystal orientation becomes challenging, particularly in wet etching processes, which complicates the manufacturing process and increases costs due to the need for multiple masking layers.
Innovation Solution
A dry etch process using a combination of passivation and etching gases, such as C4F8/O2 and SF6, with controlled RF power sources to achieve anisotropic etching, allowing for the formation of cavities with controllable profile angles and improved physical vapor deposition step coverage, reducing the need for masking layers and simplifying the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wet etching process is used to form backside cavities, then etching can be performed, but the etch profile angle cannot be precisely controlled and dependency on crystal orientation increases
Solution Approach 1:
The patent replaces the chemical-based wet etching process with a physics-based dry etching process using plasma. This substitution allows for precise control of etch profile angles through physical parameters such as RF power, gas flow rates, and pressure, eliminating the uncontrollable chemical reactions and crystal orientation dependencies inherent in wet etching.
Solution Approach 2:
The patent employs parameter changes by adjusting RF power sources, gas flow rates (C4F8 and O2), and chamber pressure to achieve desired etch profile angles. By dynamically controlling these parameters during the dry etching process, precise angular control is achieved without being constrained by crystal orientation, directly resolving the technical contradiction.
2Manufacturing precision
If multiple masking layers are used to achieve precise etch profiles, then etching precision can be improved, but process complexity and costs increase
Solution Approach 1:
The patent replaces the multi-layer masking approach with a direct physical vapor deposition method using plasma. This substitution eliminates the need for multiple masking layers by using controlled physical processes to achieve precise etch profiles directly, thereby reducing process complexity while maintaining or improving etching precision.
Solution Approach 2:
The patent extracts and removes the masking layers from the process by using a dry etching method that can achieve precise profiles without them. The etching process directly forms the desired cavity shapes through controlled plasma reactions, eliminating the intermediate masking steps and simplifying the overall manufacturing process.
3Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated, but additional problems arise in etching control
Solution Approach 1:
The patent uses parameter changes by adjusting RF power, gas flow rates, and pressure to maintain precise etching control at reduced feature sizes. These parameter optimizations enable the dry etching process to achieve the required precision for smaller features, supporting higher integration density without sacrificing etching control quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of backside cavities with controlled etch profile angles, enhances deposition coverage on cavity walls, and reduces process complexity and costs by minimizing dependency on specific crystal orientations, thus improving semiconductor device manufacturing efficiency.
Implementation Method 1
supplying a passivation gas mixture that deposits a passivation layer on a bottom surface and sidewalls of the cavity
Implementation Method 2
etching the first area of the first semiconductor substrate using an etching gas, where the etching gas is supplied concurrently with the passivation gas mixture
Data Source
AI summary
A method includes bonding a first surface of a first semiconductor substrate to a first surface of a second semiconductor substrate and forming a cavity in the first area of the first semiconductor substrate, where forming the cavity comprises: supplying a passivation gas mixture that deposits a passivation layer on a bottom surface and sidewalls of the cavity, where during deposition of the passivation layer, a deposition rate of the passivation layer on the bottom surface of the cavity is the same as a deposition rate of the passivation layer on sidewalls of the cavity; and etching the first area of the first semiconductor substrate using an etching gas, where the etching gas is supplied concurrently with the passivation gas mixture, etching the first area of the first semiconductor substrate comprises etching in a vertical direction at a greater rate than etching in a lateral direction.