Wafer Surface Etching Patterns for Warpage Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional wafers, especially those that are large-sized, insufficiently rigid, ultra-thin, or with crystal internal stress, are prone to deformation due to stress, affecting their geometric shape and quality during dicing.

Innovation Solution

A wafer processing method involving the formation of etching patterns on the surface, either inwardly recessed or outwardly protruding, to reduce the influence of internal stress and external forces, using fixture patterns and etching steps to create geometric adjustments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the wafer is made large-sized or ultra-thin to improve integration density, then the wafer becomes insufficiently rigid and prone to deformation, but reducing wafer size or thickness compromises integration density and performance

Engineering Contradiction:
Improvewafer sizeVSAvoidgeometric shape stability
Core Design Contradiction:
Volume of moving objectVSStability of the object's composition

Solution Approach 1:

The patent applies local quality by creating etching patterns at specific locations on the wafer surface rather than uniform treatment. The etching patterns are formed at stress concentration places identified through optical inspection, providing localized stress relief where needed most while preserving the overall wafer structure and size.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs preliminary action by identifying stress concentration places using optical inspection before performing the etching process. This allows the etching patterns to be precisely positioned at areas that will experience stress during subsequent processing, preventing deformation before it occurs.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If conventional etching is performed uniformly across the wafer surface, then the process is simple, but it cannot effectively address localized stress concentration and geometric warpage

Engineering Contradiction:
Improveetching process simplicityVSAvoidgeometric shape control
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent transitions from uniform etching to localized etching by identifying specific stress concentration places through optical inspection. The etching patterns are applied only at these identified locations, maintaining process simplicity while significantly improving geometric shape control by targeting the root cause of warpage.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent replaces uniform mechanical etching with a selective process guided by optical inspection. Instead of applying mechanical etching force uniformly across the entire wafer surface, the system uses optical detection to identify stress concentration areas and applies etching only there, substituting blind mechanical processing with targeted processing based on visual feedback.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20250372422A1Method of processing wafer
Publication Date: 2025.12.04 GLOBALWAFERS CO LTD
  • US20250372422A1 patent drawing
  • US20250372422A1 patent drawing
  • US20250372422A1 patent drawing

AI summary

A wafer and a wafer processing method are included. The wafer processing method includes the following steps. A wafer is provided having a first surface and a second surface opposite to the first surface. A fixture pattern is pasted on the first surface to cover a first portion of the first surface of the wafer, and a second portion of the first surface is exposed by the fixture pattern. A first etching step is performed on the second portion of the first surface to form a first etching pattern on the first surface of the wafer. The fixture pattern is removed from the first surface, and the second surface of the wafer is ground.