Wafer Excursion Detection via Die Comparison Statistics
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Solution Overview
Problem
Current semiconductor fabrication processes face challenges in detecting geometry-induced defects due to limitations in wafer geometry metrology and wafer inspection processes, which fail to capture detailed topography information and z-height variations, leading to incomplete defect identification.
Innovation Solution
A system and method that combines wafer geometry metrology processes with wafer inspection processes, using a controller with processors to apply filtering to semiconductor wafer maps, separate them into dies, generate die comparison statistics, and create excursion maps by applying inspection thresholds to detect excursions, thereby enhancing sensitivity and accuracy in defect detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wafer geometry metrology processes are used to detect topography deviations, then manufacturing precision is improved, but detailed topography information is lost
Solution Approach 1:
The patent combines wafer geometry metrology processes with wafer inspection processes into a unified system. The wafer geometry metrology provides topography deviation detection while the wafer inspection process captures detailed topography information, including z-height variations. By merging these two processes, the system achieves both manufacturing precision in detecting topography deviations and preserves detailed topography information that would otherwise be lost.
2Productivity
If wafer inspection processes are used to locate defects, then productivity is improved, but z-height and surface geometry defects are not detected
Solution Approach 1:
The patent integrates wafer inspection processes with wafer geometry metrology processes. The wafer inspection process maintains high productivity for defect detection while the incorporated wafer geometry metrology adds the capability to detect z-height and surface geometry defects. This merging allows the system to achieve both high throughput and enhanced measurement precision for geometry-related defects.
3Device complexity
If separate wafer geometry metrology and wafer inspection processes are used, then device complexity is reduced, but detection capability is incomplete
Solution Approach 1:
The patent merges wafer geometry metrology and wafer inspection processes into a single integrated characterization system. This integration maintains relative simplicity in device structure while significantly improving reliability of defect identification. The unified system can detect both topography deviations and detailed surface geometry defects, providing complete defect identification capability that neither separate process could achieve alone.
Data Source
AI summary
A system includes a controller with one or more processors and memory configured to store one or more sets of program instructions. The one or more processors are configured to execute the one or more sets of program instructions. The one or more sets of program instructions are configured to cause the one or more processors to apply filtering to a semiconductor wafer map; separate the filtered semiconductor wafer map into a plurality of dies; generate a set of die comparison statistics for the plurality of dies; generate at least one excursion map by applying at least one inspection threshold to the set of die comparison statistics; and detect at least one excursion within the at least one excursion map.