Wafer Exposure Focus-Leveling Near the Effective Region Boundary

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Solution Overview

Problem

Existing exposure systems face challenges in achieving precise focus and leveling control, particularly near the edges of wafers, leading to insufficient focus-leveling control and increased yield loss due to defocused chips.

Innovation Solution

The boundary between the focus control effective region and the exclusion region is dynamically set based on the exposure map and chip layout, allowing for flexible focus-leveling control by excluding invalid data from the focus-leveling measurement, thereby improving focus control near the wafer periphery.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If focus-leveling control is applied across the entire wafer surface, then measurement coverage is improved, but measurement precision deteriorates due to inclusion of invalid data from the periphery region

Engineering Contradiction:
Improvemeasurement coverage areaVSAvoidfocus-leveling measurement precision
Core Design Contradiction:
Area of stationary objectVSMeasurement precision

Solution Approach 1:

The wafer surface is segmented into two distinct regions: an effective region where focus-leveling measurements are valid and reliable, and an exclusion region where measurements are invalid due to peripheral effects. This segmentation allows the system to selectively process measurement data from only the effective region, thereby maintaining high measurement precision while achieving comprehensive coverage of the usable wafer area.

Inventive Principle:
Principle #1Segmentation

2Productivity

If exposure operations are performed across the entire wafer including periphery, then productivity is improved, but manufacturing precision deteriorates due to defocused chips in the exclusion region

Engineering Contradiction:
Improvewafer exposure throughputVSAvoidpattern formation precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

Different quality standards are applied to different regions of the wafer. The effective region receives full focus-leveling control and precision exposure processing, while the exclusion region is identified and excluded from precision processing. This local quality approach ensures that chips in the effective region achieve high manufacturing precision while maintaining overall productivity by clearly defining which regions can be processed with standard precision requirements.

Inventive Principle:
Principle #3Local quality

3Device complexity

If focus control exclusion region is not defined, then device complexity is reduced, but loss of substance increases due to defective chips from insufficient focus control

Engineering Contradiction:
Improvefocus control system complexityVSAvoidchip yield loss
Core Design Contradiction:
Device complexityVSLoss of substance

Solution Approach 1:

The focus control exclusion region is defined in advance before the actual exposure process begins. By pre-establishing the boundaries of the effective and exclusion regions based on wafer characteristics and exposure parameters, the system proactively prevents the formation of defective chips in the exclusion region. This preliminary action eliminates the need for complex real-time adjustments during exposure and minimizes chip yield loss without significantly increasing system complexity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12523942B2Exposure method and exposure apparatus
Publication Date: 2026.01.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12523942B2 patent drawing
  • US12523942B2 patent drawing
  • US12523942B2 patent drawing

AI summary

In a method executed in an exposure apparatus, a focus control effective region and a focus control exclusion region are set based on an exposure map and a chip area layout within an exposure area. Focus-leveling data are measured over a wafer. A photo resist layer on the wafer is exposed with an exposure light. When a chip area of a plurality of chip areas of the exposure area is located within an effective region of a wafer, the chip area is included in the focus control effective region, and when a part of or all of a chip area of the plurality of chip areas is located on or outside a periphery of the effective region of the wafer, the chip area is included in the focus control exclusion region In the exposing, a focus-leveling is controlled by using the focus-leveling data measured at the focus control effective region.