Wafer Failure Pattern Acquisition for Test Accuracy
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Solution Overview
Problem
The existing methods for electrical performance testing of wafers lack accuracy, often misdetecting chips due to issues in the test environment, leading to reduced yield and efficiency.
Innovation Solution
A failure pattern obtaining method that involves calculating vectors between failure test points, grouping similar points, separating pending failure patterns, and determining failure patterns based on occurrence times to identify and adjust test environment issues, thereby improving test accuracy and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional electrical performance testing is performed on wafer chips, then test coverage is achieved, but test accuracy deteriorates due to misdetection caused by test environment issues
Solution Approach 1:
The patent applies preliminary action by obtaining chip test result pictures and identifying failure patterns before performing the actual electrical performance testing. The system pre-processes test data to recognize failure patterns in the test environment, then uses these patterns to correct subsequent test results, thereby improving both measurement precision and reliability.
Solution Approach 2:
The patent implements feedback by using identified failure patterns to adjust and correct test results. The system continuously monitors test outcomes, compares them against known failure patterns, and applies corrections based on this feedback loop, which resolves the contradiction between achieving test coverage and maintaining test accuracy.
2Measurement precision
If comprehensive testing of all memory addresses is performed, then test coverage is improved, but testing time increases
Solution Approach 1:
The patent extracts and separates failure patterns from test data independently from the main testing process. By identifying and isolating failure patterns in a preliminary stage, the system can quickly correct results without re-testing all memory addresses, thus maintaining comprehensive test coverage while significantly reducing total testing time.
Solution Approach 2:
The system performs preliminary analysis of test data to identify failure patterns before completing full testing. This preliminary action allows the system to anticipate and correct potential failures, reducing the need for exhaustive re-testing and thereby decreasing overall testing time while maintaining coverage.
3Measurement precision
If test environment adjustments are made to improve accuracy, then test precision is improved, but test process complexity increases
Solution Approach 1:
The patent introduces failure patterns as an intermediary element between the test environment and test results. Instead of directly complicating the test process, the system uses failure patterns as a mediating layer that automatically corrects results, thereby improving precision without significantly increasing process complexity.
Solution Approach 2:
The system creates copies of failure patterns from historical or reference data and applies these copies to correct current test results. This copying approach allows precision improvement through pattern matching without requiring complex real-time adjustments to the test environment, thus maintaining process simplicity.
Data Source
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AI summary
A failure pattern obtaining method and apparatus are provided. The method includes that: a chip test result picture for a wafer is obtained, the chip test result picture being marked with a plurality of failure test points; a vector for every two points among all failure test points is calculated; a plurality of failure test points having a same vector are designated as a same group; a plurality of pending failure patterns are separated from each of groups; a failure pattern is obtained based on the plurality of the pending failure patterns. Through the above steps, the failure pattern can be accurately and rapidly obtained, and the failure pattern is used to determine whether the test equipment fails. If the failure pattern is obtained, it is determined that the test environment of the test equipment fails, and thus the tester can adjust the test environment of the test equipment (for example, modify the test program), so as to prevent the occurrence of misdetection of the test equipment, thereby improving the accuracy of the electrical test.