Automated Semiconductor Wafer Failure Pattern Detection
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Solution Overview
Problem
Current semiconductor wafer fabrication processes face challenges in achieving high yield due to natural variation, tool imperfections, contamination, and miscalibration, leading to labor-intensive and time-consuming manual failure analysis methods that are inadequate for large-scale production.
Innovation Solution
An automated system and method for detecting failure patterns in semiconductor wafer fabrication processes using knowledge-based and statistical algorithms to classify and cluster failure patterns, which are adaptive and self-learning, enabling accurate recognition and ranking of failure patterns and improving process quality and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual eyeball techniques are used for failure analysis, then engineers can examine sample wafers and classify failure patterns, but the process becomes labor-intensive and time-consuming
Solution Approach 1:
The patent replaces manual mechanical examination methods with an automated computer-based system that uses image processing and pattern recognition algorithms to analyze wafer maps, thereby eliminating labor-intensive manual inspection while maintaining classification accuracy
Solution Approach 2:
The system creates digital copies of wafer maps from test data and uses these replicated images for automated analysis, allowing multiple analyses to be performed on the same data without additional manual inspection time
2Measurement precision
If manual failure analysis methods are used, then engineers can classify failure patterns, but the methods are limited to small sub-sets of high volume wafers
Solution Approach 1:
The automated computer-based system replaces manual inspection capabilities with algorithmic image processing that can handle large volumes of wafer data, transforming the system from handling small subsets to processing high-volume production wafers
Solution Approach 2:
The system is designed to handle multiple wafer types, test data formats, and failure pattern classifications through a unified automated platform, enabling it to process diverse high-volume wafer data that manual methods could not accommodate
3Productivity
If automated systems are implemented for failure pattern detection, then analysis speed increases, but system complexity increases
Solution Approach 1:
The patent implements automated image processing and pattern recognition algorithms that perform complex analysis tasks, replacing what would require even more complex manual procedures with systematic computational methods that increase speed while managing complexity through algorithmic approaches
Data Source
AI summary
A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.