Wafer Feature Fingerprinting for Split Manufacturing Verification

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Solution Overview

Problem

In split chip manufacturing, ensuring wafer authenticity during transfer between foundries is challenging due to the risk of adversaries replacing original wafers with compromised ones, which can lead to Trojan hardware implantation.

Innovation Solution

A method and system for wafer verification using fiducial markers to capture and compare images of different wafer features, such as grain distribution, electrical test probe marks, wafer bevel edge characteristics, and grain crystallographic structure across multiple stages of manufacturing, ensuring authenticity through inline metrology and temporary, one-time identification.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If split manufacturing is used to reduce Trojan hardware risk, then chip security is improved, but wafer authenticity verification becomes more difficult during transfer between foundries

Engineering Contradiction:
Improvechip securityVSAvoidwafer authenticity verification
Core Design Contradiction:
ReliabilityVSDifficulty of detecting and measuring

Solution Approach 1:

The system performs preliminary actions by capturing images of wafer features and generating a wafer identification model at the first foundry before wafer transfer. This model is stored securely and used for verification at subsequent foundries, enabling authenticity verification without requiring complex real-time analysis during transfer.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system creates a digital copy (image model) of the wafer's physical features instead of requiring direct physical verification. This copy can be transmitted and compared electronically at subsequent foundries, making verification easier while maintaining security.

Inventive Principle:
Principle #26Copying

2Ease of manufacture

If conventional identification methods are used for wafer tracking, then manufacturing processability is improved, but vulnerability to cloning and Trojan implantation increases

Engineering Contradiction:
Improvemanufacturing processabilityVSAvoidcloning vulnerability
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The system uses locally unique features of each wafer (grain distribution, probe marks, bevel edges, crystallographic structure) as identification characteristics. These local qualities are inherently different for each wafer and difficult to replicate, providing secure identification while maintaining manufacturing processability.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system changes the identification parameter from conventional easily-copyable labels to complex physical feature patterns that are difficult to replicate. The wafer identification model captures multiple physical parameters (grain distribution, probe mark locations, bevel edge characteristics) that together create a unique fingerprint.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240170313A1Secure one-time wafer identification in split manufacturing
Publication Date: 2024.05.23 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US20240170313A1 patent drawing
  • US20240170313A1 patent drawing
  • US20240170313A1 patent drawing

AI summary

A method of wafer verification for split manufacturing is provided. The method includes capturing images of one or more different wafer features during manufacturing using a fiducial marker. The method further includes comparing the images from one stage to a next stage for at least two stages of manufacturing to verify a wafer identification based on a matching of the one of more different wafer features from the one stage to the next stage.