Wafer Flatness Defect Representation via Site Segmentation
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Solution Overview
Problem
Current methods for evaluating semiconductor wafer flatness defects are limited in accurately identifying and representing deviations from a reference plane, particularly in defining and visualizing flatness defects across the wafer surface.
Innovation Solution
A method that divides the wafer into sites, defines a reference plane, and establishes upper and lower planes based on a threshold value to identify and graphically represent flatness defects by determining points outside these planes, using a computing device to generate a graphical representation of defect locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the wafer is divided into equally sized sites for flatness evaluation, then the measurement coverage is improved, but the complexity of data processing increases
Solution Approach 1:
The wafer surface is divided into multiple equally sized sites, with each site further segmented into a grid of points. This hierarchical segmentation allows comprehensive coverage of the wafer surface while organizing data in a manageable structure that simplifies processing by localizing measurements to specific regions rather than treating the entire surface as one complex unit.
2Measurement precision
If upper and lower planes are defined with threshold values to identify flatness defects, then the defect identification accuracy is improved, but the complexity of the evaluation method increases
Solution Approach 1:
The method transforms the flatness evaluation problem by changing the reference parameter from a single reference plane to multiple threshold-based planes (upper and lower planes) spaced by a defined threshold value. This parameter transformation enables automated defect identification through simple comparison operations, improving accuracy while the systematic approach to plane definition keeps the method manageable.
3Measurement precision
If a reference plane is defined for each site using least squares method, then the flatness evaluation precision is improved, but the computational time increases
Solution Approach 1:
The least squares reference plane is pre-calculated for each site before defect identification. This preliminary action organizes the computational work in advance, creating reusable reference data that speeds up the actual defect detection process. By separating the reference plane calculation from the defect identification step, the method optimizes computational efficiency while maintaining high precision.
Data Source
AI summary
Methods are disclosed for generating a representation of flatness defects on a wafer. Data is received describing the thickness of the wafer at a plurality of points on a wafer divided into a plurality of sites. A reference plane is defined for each of the plurality of sites. For each of the sites, an upper plane and a lower plane are defined relative to the reference plane. A determination is made as to which of the plurality of points on the wafer represents a flatness defect by identifying which points are not disposed between the upper plane and lower plane. A representation is then generated depicting a location of each of the flatness defects on the wafer. In some embodiments, a single representation is generated depicting the location of flatness defects on a plurality of wafers.