Wafer Flatness Defect Representation System
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Solution Overview
Problem
Current methods for evaluating semiconductor wafer flatness defects are limited in accurately identifying and representing deviations from a reference plane, particularly in determining flatness defects on the front side of wafers, which affects their suitability for downstream applications like lithography and device fabrication.
Innovation Solution
A system and method that divides the wafer into sites, defines a reference plane for each site, and uses threshold values to determine upper and lower planes to identify and represent flatness defects by classifying points outside these planes, generating a graphical representation of defect locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional flatness evaluation methods (SFQR or SBIR) are used to calculate maximum and minimum deviations, then the flatness range is obtained for downstream application evaluation, but the precise location and visual representation of individual flatness defects on the wafer surface are not provided
Solution Approach 1:
The wafer surface is divided into multiple discrete measurement points arranged in a grid pattern, allowing individual defect identification. Each point's deviation from the reference plane is calculated independently, enabling precise location mapping of flatness defects while maintaining systematic evaluation through the segmented approach.
2Measurement precision
If the wafer surface is divided into many measurement points to improve defect detection accuracy, then the precision of flatness evaluation is improved, but the data processing complexity and time increase
Solution Approach 1:
The patent replaces complex mechanical measurement systems with optical interference methods. A laser beam creates interference fringes when reflected from the wafer surface, and these fringes are captured by a camera. The interference pattern directly encodes surface height information, allowing rapid acquisition of flatness data across the entire wafer surface without sequential mechanical scanning, thus reducing measurement time while maintaining high precision.
3Ease of operation
If visual representation of flatness defects is generated to improve defect localization, then the ease of identifying defect locations is improved, but the complexity of the evaluation system increases
Solution Approach 1:
The patent creates a visual copy or map of the wafer surface topology by processing interference fringe images. The interference pattern captured by the camera is transformed into a color-coded representation where different colors indicate different height deviations. This visual copy allows operators to quickly identify defect locations and characteristics without interpreting raw numerical data, achieving ease of operation through information visualization rather than system complexity.
Data Source
AI summary
Systems and computer-readable media having computer-executable components are disclosed for generating a representation of flatness defects on a wafer. Data is received describing the thickness of the wafer at a plurality of points on a wafer divided into a plurality of sites. A reference plane is defined for each of the plurality of sites. For each of the sites, an upper plane and a lower plane are defined relative to the reference plane. A determination is made as to which of the plurality of points on the wafer represents a flatness defect by identifying which points are not disposed between the upper plane and lower plane. A representation is then generated depicting a location of each of the flatness defects on the wafer. In some embodiments, a single representation is generated depicting the location of flatness defects on a plurality of wafers.