Wafer Frequency Response Measurement With FEOL-BEOL Capacitance Isolation
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Solution Overview
Problem
The measurement of effective capacitance in semiconductor wafer circuits is inaccurate due to the influence of short-current and parasitic capacitance from the front-end-of-line (FEOL) and back-end-of-line (BEOL) portions, which complicates the evaluation of frequency response.
Innovation Solution
A test circuit with a clock generator that generates non-overlapping clock signals to eliminate short-current and a methodology for capacitance partitioning that allows individual characterization of FEOL and BEOL capacitances, enabling accurate measurement of effective capacitance by disconnecting FEOL and BEOL portions during testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If effective capacitance is measured using conventional methods, then measurement can be performed, but measurement accuracy is poor due to short-current and parasitic capacitance interference
Solution Approach 1:
The measurement system is segmented into multiple independent measurement circuits, each dedicated to measuring specific capacitance components (FEOL capacitance, BEOL capacitance, and total capacitance). This segmentation allows isolated measurement of each component without mutual interference, thereby improving measurement accuracy despite the presence of short-current and parasitic effects.
Solution Approach 2:
The harmful short-current and parasitic capacitance effects are extracted and isolated into separate measurement paths. By using dedicated test circuits that can selectively measure only the desired capacitance component while excluding others, the harmful factors are effectively separated from the main measurement, improving accuracy.
2Measurement precision
If FEOL and BEOL portions are connected during measurement, then complete circuit functionality is maintained, but individual capacitance characterization becomes impossible
Solution Approach 1:
The measurement approach segments the capacitance measurement into separate FEOL and BEOL components through dedicated test circuits. Each circuit is configured to measure only its specific portion, enabling precise individual characterization while maintaining overall circuit functionality through separate measurement paths.
Solution Approach 2:
Dedicated test circuits act as intermediary measurement interfaces between the FEOL and BEOL portions. These intermediary circuits enable selective measurement of individual capacitance components without requiring physical disconnection, thus maintaining circuit functionality while achieving precise individual characterization.
3Measurement precision
If conventional measurement circuits are used, then device complexity is low, but measurement accuracy is compromised by parasitic effects
Solution Approach 1:
The test circuit structure is segmented into multiple specialized measurement circuits, each optimized for measuring specific capacitance components. This segmentation improves frequency response evaluation accuracy by eliminating parasitic interference, with each segment contributing to the overall measurement precision.
Solution Approach 2:
Each measurement circuit is designed with local quality optimized for its specific measurement function. The test circuits incorporate localized features such as dedicated capacitive coupling paths and isolated measurement nodes that enhance measurement accuracy for specific capacitance components while minimizing parasitic effects in each local measurement region.
Data Source
AI summary
A device for measuring a frequency response of a wafer is provided. The device includes a first oscillator, a clock generator, a first circuit, and a first driver. The first oscillator configured to provide a first signal having a first frequency. The clock generator is configured to receive the first signal and generate a first clock signal and a second clock signal having the first frequency. The first circuit on the wafer and having a first number of parallelly connected ring oscillators. The first driver is coupled to the first circuit and the clock generator, and configured to receive the first clock signal and the second clock signal, and drive the first circuit. A first portion of each ring oscillator of the first circuit is electrically disconnected from a second portion of each ring oscillator of the first circuit.