Wafer Full Edge Trimming for Tape Lamination and Positioning

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Current edge trimming processes in wafer processing, such as half-cut trimming, leave excess tape and reduce or eliminate the V-notch, making subsequent processes like taping and backside grind more difficult due to poor lamination and positioning issues.

Innovation Solution

A wafer processing method involving full edge trimming with a chuck table of smaller diameter, forming a flat portion at the periphery to facilitate taping and backside grind, and using this flat portion as a positioning means, which reduces edge chipping and improves positioning recognition.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If half-cut trimming is used, then the edge trimming process can be implemented, but the tape lamination quality deteriorates due to excess tape in suspension

Engineering Contradiction:

Improveedge trimming processVSAvoidtape lamination quality

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies full edge trimming that goes beyond the conventional half-cut approach, removing the entire edge portion including the suspension tape area. This excessive action (trimming more than half the wafer thickness) eliminates the tape lamination problem by removing the problematic edge region completely, achieving full edge trim quality.

Inventive Principle:

Principle #16Partial or excessive action

2Reliability

If edge trimming is implemented, then bonding voids are eliminated, but the V-notch positioning feature is reduced or eliminated

Engineering Contradiction:

Improvebonding qualityVSAvoidpositioning difficulty

Core Design Contradiction:

ReliabilityVSEase of operation

Solution Approach 1:

The patent performs edge trimming in a preliminary manner before the wafer is sent to following processes like half cutting and taping. By removing the edge portion first, the V-notch positioning issue is prevented from occurring in the first place, while still maintaining the bonding quality improvement from edge trimming.

Inventive Principle:

Principle #10Preliminary action

3Manufacturing precision

If full edge trimming is implemented, then tape lamination and positioning are improved, but the cutting tool complexity increases

Engineering Contradiction:

Improveedge trim qualityVSAvoidcutting tool complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent extracts and removes the problematic edge portion of the wafer completely through full edge trimming. By taking out the entire edge region rather than attempting to navigate around it with complex blade shapes, the solution simplifies the cutting tool requirements while achieving superior edge trim quality and eliminating tape lamination issues.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS10388535B1Wafer processing method with full edge trimming

Publication Date: 2019.08.20 POWERTECH TECHNOLOGY INC

AI summary

A wafer processing method uses a chuck table with smaller diameter than a semiconductor wafer to be processed. A cut through edge trimming is therefore implemented on the periphery of the semiconductor wafer to form a cut through straight side at the periphery and also form a flat portion at the periphery as a positioning means for taping and backside grind processes.