Wafer Geometry Measurement for Asymmetric Overlay Error Detection
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Solution Overview
Problem
Semiconductor fabrication processes induce significant distortions and asymmetric overlay errors in wafers, which are difficult to correct using traditional lithography methods, leading to errors in downstream processes.
Innovation Solution
A method and system that utilize high-resolution, distortion-free wafer geometry measurements to detect and quantify process-induced asymmetric signatures by calculating shape-change maps, in-plane distortion maps, and local shape curvature maps, allowing for the estimation of asymmetric overlay errors and potential process optimizations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional lithography scanner-based overlay correction strategies are used, then overlay errors can be corrected to some extent, but asymmetric overlay error signatures cannot be corrected
Solution Approach 1:
The system performs preliminary measurement of wafer geometry before fabrication processes to establish a baseline shape. By comparing pre- and post-processing geometry measurements, the system can predict asymmetric overlay errors before they affect downstream lithography processes, enabling proactive correction rather than reactive adjustment.
Solution Approach 2:
The invention introduces an intermediary measurement and analysis system that bridges the gap between fabrication processes and lithography overlay correction. This intermediary system measures wafer geometry changes, calculates shape-change maps, and provides predictive information that enables correction of asymmetric errors that traditional direct overlay measurement cannot detect.
2Measurement precision
If high-resolution wafer geometry measurements are performed before and after fabrication processes, then asymmetric components can be detected and quantified, but additional measurement steps and complexity are introduced
Solution Approach 1:
The wafer geometry measurement system performs multiple functions: it measures overall wafer shape, detects asymmetric components, calculates shape-change maps, and provides predictive information for overlay correction. By consolidating these functions into a single measurement system rather than requiring separate specialized instruments, the patent reduces overall system complexity while maintaining high measurement precision.
Solution Approach 2:
The measurement system automatically performs the complete analysis chain: acquiring geometry measurements, calculating shape-change maps, detecting asymmetric components, and estimating overlay errors. This self-service capability eliminates the need for manual intervention or multiple separate analysis steps, reducing operational complexity despite the advanced capabilities provided.
3Reliability
If process steps are optimized to prevent asymmetric distortions, then downstream overlay errors are reduced, but process complexity and monitoring requirements increase
Solution Approach 1:
The system implements feedback by measuring wafer geometry after fabrication processes, comparing it to the baseline, and using the detected asymmetric components to adjust subsequent processing parameters. This closed-loop feedback enables continuous optimization of fabrication processes to prevent asymmetric distortions before they propagate to downstream lithography steps.
Solution Approach 2:
By detecting asymmetric components early in the fabrication sequence and calculating their impact on overlay error, the system enables preliminary adjustments to process parameters before downstream lithography. This preliminary action prevents the formation of problematic asymmetric distortions rather than attempting to correct them later, simplifying overall process control.
Data Source
AI summary
Systems and methods to detect, quantify, and control process-induced asymmetric signatures using patterned wafer geometry measurements are disclosed. The system may include a geometry measurement tool configured to obtain a first set of wafer geometry measurements of the wafer prior to the wafer undergoing a fabrication process and to obtain a second set of wafer geometry measurements of the wafer after the fabrication process. The system may also include a processor in communication with the geometry measurement tool. The processor may be configured to: calculate a geometry-change map based on the first set of wafer geometry measurements and the second set of wafer geometry measurements; analyze the geometry-change map to detect an asymmetric component induced to wafer geometry by the fabrication process; and estimate an asymmetric overlay error induced by the fabrication process based on the asymmetric component detected in wafer geometry.