3D Wafer Interconnection With H-Shaped Barrier Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current head-mounted displays for augmented reality (AR) and virtual reality (VR) applications face challenges due to the use of long wires or metal interconnections, which consume space and complicate device mounting, making it difficult to produce display devices suitable for these environments.
Innovation Solution
A method involving bonding a top wafer to a bottom wafer with a first metal interconnection having a barrier layer on the bottom surface, followed by forming a dielectric layer and a second metal interconnection in the dielectric layer, where the barrier layers form a H-shape, enabling efficient metal interconnection formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If long wires or metal interconnections are used to connect DDICs to display module, then electrical connection is achieved, but space consumption increases and mounting difficulty increases
Solution Approach 1:
The patent transitions from planar interconnections to three-dimensional vertical interconnections by forming metal interconnection structures that extend through multiple die layers. The via holes and conductive plugs create vertical pathways, allowing electrical connections to be made in the Z-dimension rather than requiring long lateral wires, thereby reducing the footprint area while maintaining reliable electrical connectivity.
Solution Approach 2:
The patent implements nested interconnection structures where conductive plugs are embedded within via holes, which are themselves embedded within die layers. Multiple metal interconnection structures are nested at different vertical levels, with upper dies connected to lower dies through this nested via-plug-metal structure, enabling compact three-dimensional integration without requiring extensive lateral wiring space.
2Reliability
If long wires or metal interconnections are used to connect DDICs to display module, then electrical connection is achieved, but mounting difficulty increases
Solution Approach 1:
The patent divides the interconnection system into discrete, modular segments: individual via holes, separate conductive plugs, distinct metal interconnection layers, and separable die units. This segmentation allows each component to be independently formed, aligned, and connected, simplifying the mounting and assembly process compared to handling long continuous wires or complex planar interconnection structures.
Solution Approach 2:
By moving interconnections to the vertical dimension through via holes and conductive plugs, the patent enables straightforward stacking and bonding of die layers. The vertical alignment and bonding process is more manageable than lateral wire routing and connection, reducing mounting complexity while ensuring reliable electrical connections between display module and DDICs.
3Reliability
If barrier layers are formed at metal interconnection interfaces, then diffusion prevention is achieved, but manufacturing complexity increases
Solution Approach 1:
The barrier layer serves multiple functions simultaneously: it prevents diffusion between metal and semiconductor materials, provides a foundation for subsequent metal layer deposition, and acts as an interface layer for adhesion. This multi-functionality reduces the need for additional separate layers or processes, thereby managing manufacturing complexity while ensuring reliable diffusion prevention.
Solution Approach 2:
The patent combines the barrier layer formation with the metal interconnection formation process, where the barrier layer is deposited as part of the same sequence that forms the conductive plugs and metal interconnection structures. This merging of functions into a unified process flow reduces the total number of discrete manufacturing steps while maintaining effective diffusion prevention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces space consumption and simplifies mounting by creating a more compact and efficient semiconductor device with improved metal interconnections, enhancing the fabrication process for AR and VR display devices.
Implementation Method 1
first bonding a top wafer to a bottom wafer
Data Source
AI summary
A method for fabricating a semiconductor device includes the steps of first bonding a top wafer to a bottom wafer, in which the top wafer has a first metal interconnection including a first barrier layer exposing from a bottom surface of the top wafer. Next, a dielectric layer is formed on the bottom surface of the top wafer and then a second metal interconnection is formed in the dielectric layer and connected to the first metal interconnection, in which the second metal interconnection includes a second barrier layer and the first barrier layer and the second barrier layer include a H-shape altogether.