Wafer Holder Tape for Semiconductor Probe Testing

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Solution Overview

Problem

Current methods for testing semiconductor wafers face challenges in efficiently establishing electrical connections for probe testing, particularly when dealing with thinned wafers and stacked die configurations, which can lead to instability and reduced accuracy in quality assurance and reliability assessments.

Innovation Solution

The method involves using a wafer holder with a tape or film portion that includes openings for establishing electrical connections through conductive traces, allowing for secure mounting and testing of partial semiconductor wafers, including those with stacked die, by creating temporary conductive paths that maintain structural integrity and facilitate direct backside electrical interconnects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional mounting methods are used for probe testing, then the testing process is simple, but electrical connection stability and measurement precision deteriorate

Engineering Contradiction:
Improveelectrical connection stabilityVSAvoidmounting structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces a tape portion with conductive traces as an intermediary element between the wafer holder and the semiconductor wafer. This tape serves as a mediator that establishes stable electrical connections while accommodating thinned wafers and stacked die configurations, thereby improving measurement precision without requiring direct rigid contact

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The mounting structure is segmented into distinct functional components: the wafer holder provides mechanical support, the tape portion with openings enables electrical access, and the conductive traces provide electrical pathways. This segmentation allows each component to optimize its specific function, improving overall connection stability

Inventive Principle:
Principle #1Segmentation

2Volume of moving object

If thinned wafers and stacked die are used to minimize package size, then the semiconductor device size is reduced, but handling stability and testing reliability worsen

Engineering Contradiction:
Improvesemiconductor device sizeVSAvoidhandling stability
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent employs a flexible tape portion with openings that can adapt to thinned wafer configurations. This flexible film structure provides support and stability to thinned wafers and stacked die during handling and testing, preventing damage while maintaining the size reduction benefits

Inventive Principle:
Principle #30Flexible shells and thin films

Solution Approach 2:

The mounting structure is designed with inherent cushioning and support features that protect thinned wafers before testing begins. The tape portion and holder configuration provide pre-established protection against handling damage, ensuring reliability throughout the testing process

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Adaptability or versatility

If multiple openings are created in the tape portion for electrical access, then electrical connection capability is improved, but structural integrity and manufacturing complexity worsen

Engineering Contradiction:
Improveelectrical connection capabilityVSAvoidtape processing difficulty
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The openings in the tape portion are pre-formed before the actual probe testing process. This preliminary action allows the tape to be prepared in advance with the required electrical access points, simplifying the manufacturing process and ensuring structural integrity is maintained throughout subsequent handling and testing operations

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11694937B2Semiconductor wafer and method of probe testing
Publication Date: 2023.07.04 SEMICON COMPONENTS IND LLC
  • US11694937B2 patent drawing
  • US11694937B2 patent drawing
  • US11694937B2 patent drawing

AI summary

Implementations of methods of making a semiconductor device may include: providing a partial semiconductor wafer. The method may also include providing a wafer holder including a tape portion with one or more openings through the tape portion. The method may include mounting the partial semiconductor wafer over the one or more openings in the tape portion of the wafer holder and providing an electrical connection to the partial semiconductor wafer through the one or more openings in the tape portion during probe test.