Wafer Hybridization Compensation via Removable Planarizing Layer
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Solution Overview
Problem
Semiconductor wafers with non-planar surfaces, exhibiting 'wafer bow' or 'dishing,' pose challenges for electrical connections due to deviations in flatness, making them unsuitable for use with small pitch and height contacts, especially when stacking chips.
Innovation Solution
A method involving the formation of electrically conductive posts through a removable material, smoothing the surface, and removing the material to create a substantially planar surface, allowing for connections and stacking despite wafer bow up to 20 μm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional polishing operations are performed to reduce wafer bow, then manufacturing precision improves, but device complexity and cost increase
Solution Approach 1:
The patent introduces an intermediary planarization layer (dielectric material) between the bowed wafer and the contact structures. This layer acts as a mediator that compensates for wafer bow without requiring complex polishing operations. The layer is deposited over the entire wafer surface and then selectively removed in contact regions, providing a planar surface for contacts while accommodating the underlying wafer non-planarity.
Solution Approach 2:
The patent changes the physical state and properties of the wafer surface by depositing a dielectric material layer that modifies the surface topology. Instead of mechanically removing material through polishing, the process uses deposition to add material, fundamentally changing the approach from subtractive to additive manufacturing to achieve planarity.
2Manufacturing precision
If wafer bow is reduced through expensive polishing operations, then manufacturing precision improves, but loss of substance and cost increase
Solution Approach 1:
The dielectric planarization layer serves as an intermediary that eliminates the need for material removal. Instead of polishing away wafer material to achieve flatness, the layer is deposited over the bowed surface and selectively removed only where contacts are needed, preserving the underlying wafer material while achieving the required planarity for contact formation.
Solution Approach 2:
The planarization layer is a temporary, disposable structure that is deposited to enable contact formation and then selectively removed. This temporary layer achieves the planarization function without permanently removing valuable wafer material, effectively sacrificing a low-cost dielectric material to preserve the high-value semiconductor wafer.
3Productivity
If wafer bow is accommodated without polishing, then productivity improves, but manufacturing precision deteriorates
Solution Approach 1:
The dielectric planarization layer acts as a mediator that decouples the contact formation process from the underlying wafer non-planarity. By providing a planar surface for contact deposition and alignment, the layer enables precise contact placement without requiring time-consuming wafer polishing operations, thus maintaining both productivity and precision.
Solution Approach 2:
The planarization layer is deposited in advance before contact formation, preliminarily establishing a planar surface that facilitates subsequent contact alignment and deposition. This preliminary action eliminates the need for time-consuming polishing operations that would otherwise be required to achieve the necessary precision for contact formation.
Data Source
AI summary
A planarizing method performed on a non-planar wafer involves forming electrically conductive posts extending through a removable material, each of the posts having a length such that a top of each post is located above a plane defining a point of maximum deviation for the wafer, concurrently smoothing the material and posts so as to form a substantially planar surface, and removing the material. An apparatus includes a non planar wafer having contacts thereon, the wafer having a deviation from planar by an amount that is greater than a height of at least one contact on the wafer, and a set of electrically conductive posts extending away from a surface of the wafer, the posts each having a distal end, the distal ends of the posts collectively defining a substantially flat plane.