Miniature Wafer Identification Mark Placement for Die Yield
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Solution Overview
Problem
Conventional identification marks on semiconductor wafers are excessively large, limiting the number of dies per wafer and being prone to degradation, which affects traceability and yield in semiconductor fabrication.
Innovation Solution
The implementation of miniature identification marks that are strategically positioned closer to the wafer edge, avoiding areas that may cause peeling issues, and are designed to be smaller in size and arranged in a way that increases the usable die area by being offset from the alignment notch, thus allowing for more efficient die placement and reduced risk of mark degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional identification marks are used on semiconductor wafers, then the marks are large enough to be readable, but the usable die area is reduced and the marks are prone to degradation
Solution Approach 1:
The identification mark size is reduced from conventional large dimensions to miniature dimensions (e.g., 3-5mm width, 0.5-1.5mm height), changing the physical parameters of the mark while maintaining readability through strategic positioning and contrast enhancement
Solution Approach 2:
The identification mark is positioned in the peripheral region of the wafer rather than the central die area, utilizing the radial dimension from center to edge to place marks in previously underutilized space, thereby increasing usable die area while maintaining mark visibility
2Ease of operation
If conventional identification marks are positioned on the wafer, then the marks are easily accessible, but they are located in areas prone to peeling and degradation
Solution Approach 1:
Different regions of the wafer are assigned different functions: the central region is dedicated to die placement with high quality requirements, while the peripheral region is designated for identification marks where accessibility is prioritized. The mark positioning accounts for local variations in stress and peeling risk by avoiding specific high-risk zones
Solution Approach 2:
The identification mark position is predetermined and optimized before wafer processing begins, selecting locations that balance accessibility with long-term stability considerations, avoiding regions known to be prone to peeling during subsequent fabrication steps
3Productivity
If more dies are placed per wafer, then productivity increases, but the identification marks become harder to read and locate
Solution Approach 1:
The wafer surface is segmented into distinct functional zones: a central die region for high-density device placement and a peripheral identification region for marks. This spatial segmentation allows independent optimization of each zone, enabling high die density in the center while maintaining clear, accessible identification marks in the periphery
Data Source
AI summary
A wafer includes a first face having a first center, and a second face having a second center. The first and second centers are each arranged on a central axis, which passes through the first face and the second face. The first face and the second face adjoin one another at a circumferential edge. An alignment notch is disposed along the circumferential edge, and extends inwardly from the circumferential edge by an alignment notch radial distance. The alignment notch radial distance is less than a wafer radius as measured from the first center to the circumferential edge. A die region includes an array of die arranged in rows and columns and is circumferentially bounded by a die-less region which is devoid of die. A first identification mark including a string of characters is disposed entirely in the die-less region to a first side of the alignment notch.