Wafer Image Simulation for Self-Aligned Double Patterning Hotspot Correction
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Solution Overview
Problem
Self-aligned double patterning techniques face challenges in accurately reproducing complex patterns on integrated circuits due to diffractive effects during photolithographic processes, leading to defects such as extra unwanted features or missing features in manufactured devices.
Innovation Solution
A computing system implements a self-aligned double-patterning tool that simulates a wafer image using a mandrel mask and a block mask, estimates dummy sidewalls and contours, identifies hotspots for pattern correction, and modifies the target image to prioritize edge adjustments in optical proximity correction, thereby improving pattern fidelity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If self-aligned double patterning is used to manufacture integrated circuits, then manufacturing precision can be improved, but diffractive effects during photolithographic processes cause unwanted features or missing features
Solution Approach 1:
The patent performs preliminary simulation of the photolithographic process before actual manufacturing to identify and correct potential pattern defects. By simulating the wafer image formation and detecting hotspots in advance, the system can pre-adjust the mask patterns to compensate for diffractive effects, thereby preventing unwanted features from forming during actual production.
Solution Approach 2:
The patent implements a feedback mechanism where the simulated wafer image is compared against the target pattern to identify hotspots. This feedback information is then used to iteratively adjust and optimize the mask patterns, allowing the system to learn from simulation results and improve pattern accuracy by correcting identified defects in subsequent iterations.
2Manufacturing precision
If comprehensive simulation and correction processes are implemented, then pattern fidelity is improved, but computational time and complexity increase
Solution Approach 1:
Instead of uniformly processing the entire pattern, the patent identifies and focuses computational resources on specific problematic areas called hotspots. By detecting and correcting only the local regions where diffractive effects cause unwanted features or missing features, the system achieves high pattern fidelity without the need for comprehensive processing of the entire pattern, thereby reducing overall computational time.
Solution Approach 2:
The patent divides the complex photolithographic simulation and correction process into distinct segments: pattern decomposition into mandrel and spacer layers, separate simulation of each layer's contribution to the final wafer image, identification of hotspots in the combined image, and targeted correction. This segmentation allows each step to be optimized independently and reduces the computational complexity of the overall process.
Data Source
AI summary
This application discloses a computing system to simulate a wafer image based on a mandrel mask and a block mask to be utilized to print a final wafer image on a substrate. To simulate the wafer image the computing system can estimate dummy sidewalls based on the mandrel mask, estimate contours of the block mask, and determine the simulated wafer image based on differences between the dummy sidewalls and the estimated contours of the block mask. The computing system can compare the simulated wafer image against a target wafer image in a layout design to identify hotspots where the simulated wafer image deviates from the target wafer image. Based on the identified hotspots, the computing system can modify the target wafer image in the layout design, prioritize edge modification in a subsequent optical proximity correction process, or modify computation of image error, which drives the optical proximity correction process.