Wafer Inlay Process for Replacing Defective Device Regions

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Solution Overview

Problem

The manufacturing of stacked device chips is hindered by defective semiconductor devices, leading to reduced yield due to the inclusion of defective devices in the stacking process, and existing methods to remove defective devices are inefficient, requiring labor-intensive adjustments to ensure proper fit of non-defective chips in the wafer spaces.

Innovation Solution

A method involving the removal of defective device regions from wafers, enlargement of the resulting spaces by heating, and inlaying non-defective device chips, ensuring precise fit without the need for subsequent adjustments, thereby preventing the production of defective stacked device chips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If defective device regions are cut out from the wafer, then the yield of stacked device chips is improved, but the spaces left in the wafer cannot be precisely controlled to match device chip dimensions

Engineering Contradiction:

Improveyield of stacked device chipsVSAvoiddimensional precision of spaces

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies thermal expansion by heating the wafer to enlarge the spaces created by removing defective device regions. This parameter change (temperature increase) transforms the dimensional characteristics of the spaces, allowing them to expand to precise target dimensions that match the device chips to be inlaid, thereby resolving the dimensional precision issue while maintaining the yield improvement benefit

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent performs the enlargement of spaces through heating before the inlaying process. This preliminary action ensures that the spaces are pre-adjusted to the correct dimensions before device chips are placed, eliminating the need for subsequent dimensional adjustments and streamlining the manufacturing process

Inventive Principle:

Principle #10Preliminary action

2Reliability

If device chips are inlaid into spaces left after removing defective devices, then the wafer is free of defective devices, but labor-intensive adjustments are required to ensure proper fit

Engineering Contradiction:

Improvedefect-free waferVSAvoidmanufacturing process complexity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

By heating the wafer to induce thermal expansion, the spaces are automatically enlarged to precise target dimensions. This parameter change eliminates the need for manual or labor-intensive adjustments during the inlaying process, as the thermal expansion naturally achieves the correct fit between device chips and spaces

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent replaces mechanical adjustment processes with thermal expansion. Instead of using mechanical means to adjust and fit device chips into spaces, the process uses controlled heating to automatically enlarge spaces to the correct dimensions, substituting a thermal field for mechanical operations and thereby reducing labor intensity

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method ensures the production of wafers and stacked device chips free of defective devices, enhancing yield by eliminating the need for labor-intensive adjustments and ensuring reliable chip integration.

Implementation Method 1

an enlarging step of enlarging a removed region formed in the wafer by removing the defective device region from the wafer

Methodology Applied

Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS12087589B2Method of manufacturing wafer and method of manufacturing stacked device chip

Publication Date: 2024.09.10 DISCO CORP

AI summary

A method of manufacturing a wafer includes a wafer preparing step of preparing a wafer having semiconductor devices formed in a plurality of respective areas demarcated thereon by a plurality of intersecting streets, a removing step of removing from the wafer a defective device region including a semiconductor device determined as a defective product among the semiconductor devices formed on the wafer, an enlarging step of enlarging a removed region formed in the wafer by removing the defective device region from the wafer, and an inlaying step of inlaying a device chip including a non-defective semiconductor device that is functionally identical to the semiconductor device determined as the defective product, in the enlarged removed region.