Wafer Structure with Integrated Inkjet Chip for Cost Reduction
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Solution Overview
Problem
Conventional inkjet chip manufacturing using semiconductor processes on small wafers (<6 inches) results in high costs due to additional nozzle fabrication steps and limited yield, making it difficult to achieve higher resolution and faster printing speeds while maintaining competitiveness in the market.
Innovation Solution
A wafer structure with a silicon substrate fabricated by a semiconductor process, where inkjet chips with integral ink-drop generators, including an ink-supply chamber and nozzle, are directly formed, allowing for higher resolution and performance, and enabling the production of inkjet chips with varying printing swath sizes on a larger substrate, such as 12 inches, to reduce manufacturing costs and increase yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional inkjet chip manufacturing uses small wafer structures (less than 6 inches) with separate nozzle plate fabrication, then the manufacturing process can be completed, but the manufacturing cost increases and manufacturing precision requirements become excessively high
Solution Approach 1:
The patent merges the nozzle structure and ink-supply chamber into a single integrated ink-drop generator fabricated by semiconductor processes on the same wafer substrate. This eliminates the separate nozzle plate fabrication and alignment steps, resolving the contradiction by making the manufacturing process easier (reducing cost and complexity) while maintaining high precision through integrated fabrication.
Solution Approach 2:
The wafer substrate serves multiple functions: it acts as both the base for ink-drop generators and the substrate for fabricating nozzles integrated within those generators. This multi-functionality eliminates the need for separate nozzle plates, reducing manufacturing cost and simplifying the process while achieving precise alignment through single-substrate fabrication.
2Productivity
If conventional inkjet chip manufacturing uses small wafer structures (less than 6 inches), then the manufacturing process is manageable, but the productivity is limited due to restricted wafer area
Solution Approach 1:
The patent changes the wafer size parameter from less than 6 inches to 12 inches, doubling the available fabrication area. This parameter change directly increases productivity by allowing more ink-drop generators to be fabricated on each wafer, while the integrated nozzle design ensures that the increased area is fully utilized without proportionally increasing complexity.
3Reliability
If inkjet chips are designed for higher resolution and faster printing speed with larger printing swath, then the printing performance improves, but the manufacturing cost increases due to limited wafer area utilization
Solution Approach 1:
The patent transitions from small (<6 inch) to large (12 inch) wafers, utilizing the additional spatial dimension to accommodate larger printing swaths and higher resolution requirements. This dimensional change allows multiple high-performance inkjet chips to be fabricated on a single large wafer, maintaining cost-effectiveness while achieving superior printing quality through increased chip density and larger active areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for more efficient use of wafer space, reducing manufacturing costs and enabling higher resolution and faster printing speeds by integrating ink-supply chambers and nozzles in the semiconductor process, thereby improving the competitiveness of inkjet chips.
Implementation Method 1
The ink-drop generator includes a resistance heating layer formed on the thermal-barrier layer, a part of a protective layer formed on the resistance heating layer, and the barrier layer formed on the protective layer. The ink-supply chamber has a bottom in communication with the protective layer, and a top in communication with the nozzle.
Data Source
AI summary
A wafer structure is disclosed and includes a chip substrate and at least one inkjet chip having plural ink-drip generators. Each ink-drop generator includes a thermal-barrier layer, a resistance heating layer and a protective layer. The thermal-barrier layer is formed on the chip substrate, the resistance heating layer is formed on the thermal-barrier layer, a part of the protective layer is formed on the resistance heating layer, and the barrier layer is formed on the protective layer. The ink-supply chamber has a bottom in communication with the protective layer, and a top in communication with the nozzle. The thermal-barrier layer has a thickness of 500˜5000 angstroms, the protective layer has a thickness of 150˜3500 angstroms, the resistance heating layer has a thickness of 100˜500 angstroms, the resistance heating layer has a length of 5˜30 microns, and the resistance heating layer has a width of 5˜10 microns.