Wafer Level Interconnects via Trench Etching
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Solution Overview
Problem
Current wafer level packaging techniques face challenges in accommodating high pin counts and high input/output requirements due to space limitations, leading to increased complexity and cost, with issues such as air trapping, cracking, and inconsistent electrical connections.
Innovation Solution
The method involves forming trenches and channels in a molded wafer to create openings for interconnects, allowing for the formation of continuous wire bonds that extend through the mold material, reducing processing time and complexity by avoiding sequential via formation and plating processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If wafer level packaging is used to reduce device size, then package size and interconnect length are reduced, but the number and pitch of interconnect elements are restricted
Solution Approach 1:
The patent transitions from planar interconnect arrangement (2D) to three-dimensional interconnect structure by forming vias that extend vertically through the molded wafer. This allows interconnect elements to be positioned in multiple dimensions, increasing interconnect capacity without increasing the device footprint.
Solution Approach 2:
The patent divides the interconnect structure into multiple segments: bond pads on the die, vias through the molded wafer, and external interconnect elements. This segmentation allows each component to be optimized independently, enabling high pin count while maintaining compact package size.
2Manufacturing precision
If sequential via formation by ablation or drilling is used, then individual vias can be formed, but processing time increases
Solution Approach 1:
The patent combines multiple via formation operations into a single parallel etching process. Instead of forming vias sequentially through ablation or drilling, the etching process simultaneously creates multiple vias across the wafer, dramatically increasing productivity while maintaining consistent via dimensions through controlled etching parameters.
3Productivity
If etching process is used to form vias simultaneously, then processing time is reduced, but via size consistency and dense distribution are difficult to achieve
Solution Approach 1:
The patent optimizes etching process parameters including etchant composition, temperature, pressure, and exposure time to achieve consistent via dimensions. By carefully controlling these parameters, the etching process produces uniform vias with precise dimensions and consistent spacing, enabling dense via distribution while maintaining high productivity.
4Adaptability or versatility
If interconnects are positioned outside die footprint, then number and pitch of interconnects increase, but processing complexity and cost increase
Solution Approach 1:
The molded wafer serves multiple functions: it provides structural support, electrical insulation, and a template for via formation. The same molding process that creates the package structure also defines the via locations and dimensions, eliminating the need for separate via formation tooling and reducing processing complexity.
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 2C
AI summary
Semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a method of manufacturing a semiconductor device includes forming a plurality of first side trenches (210) to an intermediate depth in a molded portion of a molded wafer (110) having a plurality of dies (106) arranged in rows and columns. The method also includes removing material from a second side (220) of the molded portion at areas aligned with the first side trenches, wherein removing the material forms openings (224) through the molded portion. The method further includes forming a plurality of electrical contacts at the second side of the molded portion at the openings and electrically connecting the second side contacts to corresponding bond-sites (109) on the dies.