Wafer-to-Wafer Interconnection via Segmented Etching Stop Layers

Solution Overview

Problem

Long-time etching for deeper TSVs in 3D IC technology can lead to electric charging on metal etching stop layers, causing arcing and wafer damage, which affects the yield and stability of wafer-to-wafer interconnection structures.

Innovation Solution

A method is introduced that includes forming a first etching stop layer with a pre-formed void on a substrate, allowing for shorter etching times by aligning a second etching stop layer with the void, thereby preventing electric charging and wafer damage, and involves depositing metal layers, patterning, and covering with insulation layers to create a stable interconnection structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If long time etching is performed for deeper TSV, then the deeper TSV can be formed, but electric charging occurs on metal etching stop layer causing arcing and wafer damage

Engineering Contradiction:

ImproveTSV depthVSAvoidwafer integrity

Core Design Contradiction:

Length of stationary objectVSReliability

Solution Approach 1:

The etching stop layer is divided into two separate portions: a first etching stop layer portion and a second etching stop layer portion. This segmentation allows the etching process to be interrupted before reaching the first etching stop layer, preventing the accumulation of electric charge that would otherwise occur during prolonged etching to reach a single deep stop layer. The segmented structure enables formation of deep TSVs while maintaining wafer integrity by reducing continuous etching time.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first etching stop layer portion is positioned at a shallower depth within the substrate, serving as an intermediate stopping point during the etching process. This preliminary stop layer allows the etching to be halted before excessive depth is reached, preventing the harmful effects of long-time etching such as electric charging and arcing, while still enabling subsequent formation of deeper TSVs through additional processing steps.

Inventive Principle:

Principle #10Preliminary action

2Length of stationary object

If long time etching is performed for deeper TSV, then the deeper TSV can be formed, but arcing occurs due to electric charging

Engineering Contradiction:

ImproveTSV depthVSAvoidarcing

Core Design Contradiction:

Length of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The etching stop layer is divided into two separate portions: a first etching stop layer portion and a second etching stop layer portion. This segmentation allows the etching process to be interrupted before reaching the first etching stop layer, preventing the accumulation of electric charge that would otherwise occur during prolonged etching to reach a single deep stop layer. The segmented structure enables formation of deep TSVs while maintaining wafer integrity by reducing continuous etching time.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first etching stop layer portion is positioned at a shallower depth within the substrate, serving as an intermediate stopping point during the etching process. This preliminary stop layer allows the etching to be halted before excessive depth is reached, preventing the harmful effects of long-time etching such as electric charging and arcing, while still enabling subsequent formation of deeper TSVs through additional processing steps.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the time required for etching deeper openings, prevents electric charging and arcing, and enhances the yield and stability of wafer-to-wafer interconnection structures by avoiding damage during the etching process.

Implementation Method 1

depositing a metal layer

Methodology Applied

Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

forming an oxide liner on a sidewall of the first opening and a sidewall of the second opening

Methodology Applied

Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 3

conformally depositing a barrier layer on an inner surface of the first opening and an inner surface of the second opening

Methodology Applied

Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 4

plating a metal material on the second surface of the first substrate, wherein the first opening and the second opening are filled with the metal material

Methodology Applied

Scientific EffectElectroplating: Electroplating

Data Source

PatentUS11488840B2Wafer-to-wafer interconnection structure and method of manufacturing the same

Publication Date: 2022.11.01 NAN YA TECH

AI summary

A method of manufacturing a wafer-to-wafer interconnection structure includes forming a first etching stop layer with at least two portions on a first surface of a first substrate, and forming a void in one portion of the first etching stop layer. A second etching stop layer is formed on a first surface of a second substrate, and then the first surfaces of the first substrate and the second substrate are bonded, wherein the second etching stop layer is aligned to the void. By using the first and the second etching stop layers as etching stop layers, a first opening is formed from a second surface of the first substrate into the first substrate, and a second opening is formed through the void to the second substrate. A first TSV (through silicon via) is formed in the first opening, and a second TSV is formed in the second opening.