Wafer Interconnection via Hard Mask Sidewall Protection
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Solution Overview
Problem
The current process of forming metal interconnections between wafers in semiconductor devices requires three photolithography and three etching processes, making it complex and costly.
Innovation Solution
A manufacturing method that involves forming a first opening through a passivation layer and a substrate, followed by a hard mask layer formation, and then performing maskless etching to create second and third openings, eliminating the need for additional photolithography and etching steps, thereby simplifying the process and reducing production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If three photolithography and three etching processes are used to form openings for interconnection, then the interconnection between wafers can be achieved, but the process becomes complicated and production cost increases
Solution Approach 1:
The patent combines multiple etching steps into a single etching process by using a specially designed hard mask pattern that defines all necessary opening locations (first, second, and third openings) simultaneously. This merging of steps reduces process complexity while maintaining the required interconnection reliability between wafers.
Solution Approach 2:
The patent performs preliminary patterning of the hard mask layer to predefine the positions and shapes of all required openings before the actual etching process. This preliminary action allows a single etching step to create multiple openings that would otherwise require separate photolithography and etching cycles, thereby simplifying the overall process.
2Reliability
If three photolithography and three etching processes are used to form openings for interconnection, then the interconnection between wafers can be achieved, but production cost increases
Solution Approach 1:
The patent merges multiple photolithography and etching steps into a reduced process sequence by using a hard mask-based approach that eliminates the need for multiple photomasks. This consolidation directly reduces production costs while maintaining interconnection reliability through precise mask-defined opening patterns.
Solution Approach 2:
The patent uses a disposable hard mask layer that is patterned to define all opening locations and then removed after serving its masking function. This approach eliminates the need for expensive multiple photomasks and their associated alignment processes, reducing production cost while maintaining manufacturing reliability.
3Manufacturing precision
If multiple photomasks are used for forming openings, then precise opening positions can be achieved, but the number of photomasks and process steps increases
Solution Approach 1:
The patent performs preliminary patterning of the hard mask layer to predefine the positions and shapes of all required openings (first, second, and third openings) in a single step. This preliminary action achieves precise opening positions through hard mask pattern definition while reducing the total number of process steps by eliminating subsequent photolithography cycles.
Solution Approach 2:
The patent combines the functions of multiple photomasks into a single hard mask pattern that simultaneously defines all opening locations. This merging maintains manufacturing precision through accurate mask patterning while reducing process complexity by eliminating the need for multiple sequential photolithography and etching steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the process by eliminating one photomask and reducing production costs while maintaining effective electrical connection between metal layers in the wafers.
Implementation Method 1
forming a hard mask layer, wherein the hard mask layer covers at least a sidewall surface of the first opening
Implementation Method 2
in the etching process for forming the second opening, an etching rate of the passivation layer is smaller than an etching rate of the hard mask layer
Implementation Method 3
forming an interconnection layer, wherein the interconnection layer is electrically connected to the second metal layer and the first metal layer via the first opening, the second opening and the third opening
Data Source
AI summary
A manufacturing method of a semiconductor device is disclosed, including: providing a first wafer and a second wafer that are bonded, a back surface of the first substrate of the first wafer is provided with a passivation layer; performing a photolithography and etching process to form a first opening; forming a hard mask layer, the hard mask layer covers at least a sidewall surface of the first opening; performing an etching process to form a second opening; performing a photolithography and etching process to form a third opening; and forming an interconnection layer. A back surface of a first substrate is provided with a passivation layer, after a first opening is formed, a hard mask layer is formed on a sidewall surface of the first opening, and a maskless etching process is performed to form a second opening, thereby simplifying the process, eliminating one photomask and reducing the production cost.