Low-Temperature Wafer Interconnections for Clean CMP Bonding
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Solution Overview
Problem
Existing wafer bonding processes, such as direct bond hybridization (DBH), face challenges when using low melting point metals like Indium due to high processing temperatures and contamination issues during chemical-mechanical polishing (CMP), leading to poor interconnectivity and bond strength.
Innovation Solution
A method for manufacturing wafer interconnections using low melting point metals like Indium, involving the formation of metal posts through plating within a photoresist pattern mold, followed by oxide layer deposition at a temperature below the melting point of the metal, and chemical-mechanical polishing to planarize the surface, thereby avoiding deformation and contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If direct bond hybridization (DBH) process is used to create wafer interconnections, then strong bond strength is achieved, but low melting point metals like Indium melt and deform due to high processing temperatures exceeding 225 degrees Celsius
Solution Approach 1:
The patent changes the temperature parameter of the bonding process from conventional high temperature (>225°C) to low temperature (<150°C). This is achieved by modifying the process sequence: forming oxide layers before creating metal posts, using low melting point metals (In, Ga, Sn, Pb, or their alloys) that remain stable at low temperatures, and optimizing the bonding conditions to achieve strong adhesion without thermal damage. This parameter change resolves the contradiction by enabling strong bonding while preventing metal deformation.
2Manufacturing precision
If chemical-mechanical polishing (CMP) is applied to planarize the wafer surface, then planar surfaces are achieved for bonding, but low melting point interconnection metals are contaminated on the oxide bonding surface
Solution Approach 1:
The patent extracts or removes the problematic low melting point metal posts from the bonding surface area before performing CMP. Specifically, the metal posts are formed to extend through the oxide layer, and the bonding interface is prepared on the oxide surface without the metal posts present. This prevents the metal posts from being contaminated during CMP while still allowing them to serve their interconnection function after bonding.
Solution Approach 2:
The patent performs preliminary actions by forming the oxide layer and preparing the bonding surface before creating the metal posts. The oxide layer is deposited, planarized via CMP, and cleaned to ensure a contamination-free bonding surface. Only after these preliminary steps are complete are the metal posts formed, ensuring that the critical bonding interface remains free from metal contamination throughout the process.
3Productivity
If typical plating techniques are used to fill fine pitch arrays, then interconnections are formed, but non-uniformity in the fine pitch arrays leads to poor interconnectivity
Solution Approach 1:
The patent introduces an intermediary structure - a sacrificial layer or mold material - to facilitate uniform metal post formation in fine pitch arrays. The process involves depositing a conformal layer, patterning it to define the fine pitch array locations, and then using this patterned layer as a mold or template for uniform metal deposition. This intermediary structure ensures that even at fine pitch dimensions, the metal posts are uniformly formed with consistent dimensions and spacing, resolving the non-uniformity issue.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the effective manufacturing of high yield fine pitch arrays for interconnections using low melting point metals like Indium, while maintaining the integrity of the wafer and achieving strong bond strength without deforming the low melting point materials.
Implementation Method 1
forming posts on two wafers by electroplating on a metal seed layer through a plating mold of patterned photoresist (PR)
Implementation Method 2
A layer of SiO2 is then deposited over the metal structure
Implementation Method 3
The surfaces are then planarized (i.e. made planar), for example, by using a chemical-mechanical polishing (CMP) process
Implementation Method 4
Typical wafer bonding processes involve connecting wafers using direct bond hybridization (DBH or Direct Bond Interconnection)
Data Source
Figure 1A~1B
Figure 2~3
Figure 4~5
AI summary
A method of manufacturing an array of planar wafer level metal posts includes plating an array of posts within a photoresist (PR) pattern mold on a substrate of a first wafer. Stripping the PR pattern mold from the substrate and array of posts. Applying an oxide layer, at a temperature of below 150 degrees Celsius, over a surface of the first wafer. Applying chemical-mechanical polishing (CMP) to planarize the oxide layer and the array of posts.