Wafer Scale Testing Using Two-Signal JTAG Interface
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Solution Overview
Problem
Current wafer testing methods using the IEEE 1149.1 serial interface require multiple contacts per die, leading to high costs and limited bandwidth, as they typically need 5 contacts per die and operate at low frequencies, making it inefficient for testing a large number of die on a wafer.
Innovation Solution
A high-speed, two-signal test interface utilizing simultaneously bidirectional transceiver (SBT) technology to communicate IEEE 1149.1 signals between a tester and die, allowing for simultaneous bidirectional data transfer and independent clocking of each test channel to reduce the number of contacts and increase testing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the IEEE 1149.1 serial interface is used for wafer testing, then standardized test interface is achieved, but the number of contacts per die increases to 5 and bandwidth is limited
Solution Approach 1:
The patent combines multiple test signals (TDI, TDO, TMS, TRST) into a single bidirectional data line. The SBT circuit enables full-duplex communication where data can be transmitted in both directions simultaneously over one contact, reducing the required contacts per die from 5 to 2 while maintaining IEEE 1149.1 functionality
Solution Approach 2:
The patent introduces time-division multiplexing and simultaneous bidirectional transmission to add a temporal dimension to the single data line. By allowing data to flow in both directions at the same time and using different clock frequencies for transmit and receive operations, the system achieves multi-signal communication through a single contact
2Adaptability or versatility
If the IEEE 1149.1 serial interface is used for wafer testing, then standardized test interface is achieved, but the testing bandwidth is limited due to low operating frequency
Solution Approach 1:
The patent implements dynamic clocking where the master and slave devices can operate at different clock frequencies. The master device clock and slave device clock can be independently adjusted, allowing the system to optimize bandwidth by running receive operations at higher frequencies than transmit operations, thereby increasing overall testing speed while maintaining standardized interface compatibility
3Reliability
If multiple contacts per die are used for testing, then complete IEEE 1149.1 signal transmission is achieved, but the testing cost increases and the number of die that can be tested in parallel is limited
Solution Approach 1:
The patent merges multiple signal paths into a single bidirectional data line using SBT circuitry. By combining TDI and TDO into one physical contact with simultaneous bidirectional capability, and reducing TMS and TRST to control signals, the system maintains complete IEEE 1149.1 functionality while reducing contacts per die from 5 to 2, thereby lowering probe card complexity and testing cost
Solution Approach 2:
The single bidirectional data line serves multiple functions: it carries both transmit and receive data, replaces separate TDI and TDO lines, and works with standardized IEEE 1149.1 protocols. This multi-functionality allows the same contact to perform what previously required separate dedicated lines, reducing overall contact requirements while maintaining full test capability
Data Source
AI summary
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuity, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.