Wafer Laminate Adhesive Etching for Low-Resistance Through Electrodes
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Solution Overview
Problem
In the WOW process for manufacturing semiconductor devices, the formation of through electrodes via reactive ion etching on adhesive layers leads to side etching, resulting in bowing shapes and increased leakage current paths, which in turn cause variations in resistance values between semiconductor elements.
Innovation Solution
A method involving the use of a wafer laminate with a specific adhesive layer thickness and a polymerizable group-containing polyorganosilsesquioxane, where the adhesive layer is formed with a thickness of 0.5 to 4.5 μm and etched at a rate of 1 to 2 μm/min, and through electrodes are formed by reactive ion etching with a conductive material, reducing side etching and achieving low wiring resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reactive ion etching is performed on the adhesive layer to form through electrodes, then through electrodes can be formed to electrically connect semiconductor elements in different wafers, but side etching occurs on the adhesive layer surface forming bowing shapes that create leakage current paths
Solution Approach 1:
The patent changes the physical and chemical parameters of the adhesive layer by specifying precise thickness (0.5 to 4.5 μm) and using polymerizable group-containing polyorganosilsesquioxane as the adhesive material. These parameter changes optimize the etching characteristics to achieve a etching rate of 1 to 2 μm/min, which prevents side etching and bowing shape formation while maintaining reliable electrical connections through the through electrodes
Solution Approach 2:
The patent uses polymerizable group-containing polyorganosilsesquioxane as a specialized adhesive material that combines organic and inorganic components. This composite material provides both adequate adhesion strength and controlled etching characteristics, enabling the formation of through electrodes without excessive side etching or bowing shape formation
2Productivity
If the adhesive layer is made thinner to reduce etching time, then productivity increases, but the adhesive may not provide sufficient bonding strength
Solution Approach 1:
The patent optimizes the adhesive layer thickness to a specific range (0.5 to 4.5 μm) that balances etching speed and bonding strength. This parameter optimization enables fast etching (1 to 2 μm/min) while maintaining adequate adhesive bonding strength to hold the wafer laminate structure together during and after the etching process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the variation in resistance values and achieves low wiring resistance between semiconductor elements by minimizing side etching and ensuring efficient electrical connections, thereby enhancing the performance of semiconductor devices.
Implementation Method 1
the hole needs to be formed by reactive ion etching in the hall forming to penetrate the upper wafer and the adhesive layer lying immediately under the upper wafer
Implementation Method 2
use of an adhesive is conceivable for bonding the wafers to be multilayered
Data Source
AI summary
An object of the present invention is to provide a technique suitable for achieving low wiring resistance and reducing a variation in the resistance value between semiconductor elements to be multilayered in a method of manufacturing a semiconductor device in which the semiconductor elements are multilayered through laminating semiconductor wafers via an adhesive layer. The method of the present invention includes first to third processes. In the first process, a wafer laminate Y is prepared, the wafer laminate Y having a laminated structure including a wafer 3, wafers 1T with a thickness from 1 to 20 um, and an adhesive layer 4 with a thickness from 0.5 to 4.5 μm interposed between a main surface 3a of the wafer 3 and a back surface 1b of the wafer 1T. In the second process, holes extending from the main surface 1a of the wafer 1T and reaching a wiring pattern of the wafer 3 are formed by a predetermined etching treatment. In the third process, the holes are filled with a conductive material to form through electrodes. The adhesive layer 4 has an etching rate of 1 to 2 μm/min in dry etching performed using an etching gas containing CF4, O2, and Ar at a volume ratio of 100:400:200 under predetermined conditions.