Device Wafer Lamination Using Peripheral Line Alignment
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Solution Overview
Problem
Existing methods for aligning and laminating semiconductor device wafers require photolithography processes to form alignment marks, increasing manufacturing costs and reducing the effective area for semiconductor devices.
Innovation Solution
A laminated device wafer forming method that aligns and laminates semiconductor device wafers without alignment marks by using predetermined lines on the wafer peripheries, adjusting relative positions through imaging, and omitting photolithography processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If alignment marks are formed using photolithography process, then alignment precision between device wafers is improved, but manufacturing cost increases and effective area for semiconductor devices decreases
Solution Approach 1:
The invention extracts the alignment function from the device regions and relocates it to the peripheral regions of the wafers. By using peripheral regions for alignment marks and predetermined lines, the device regions are freed from alignment-related overhead, reducing the effective area loss while maintaining alignment precision.
Solution Approach 2:
The wafer surface is segmented into device regions and peripheral regions with distinct functions. The peripheral region contains alignment marks and predetermined lines for alignment, while the device region is dedicated solely to semiconductor device formation, optimizing both alignment precision and effective device area.
2Manufacturing precision
If alignment marks are formed within rectangular regions corresponding to device chips, then alignment precision is improved, but the effective area for semiconductor devices decreases
Solution Approach 1:
The alignment function is extracted from the device regions and placed in the peripheral regions. Alignment marks and predetermined lines are positioned in the peripheral region, completely separating the alignment function from the device formation area, thus maximizing the effective area for semiconductor devices.
Solution Approach 2:
The alignment reference is moved from the two-dimensional device region to the peripheral boundary region. By using predetermined lines formed in the peripheral region and referencing them during lamination, the alignment process utilizes the peripheral dimension of the wafer, freeing up the central device area.
3Manufacturing precision
If photolithography process is used to form alignment marks, then alignment precision is improved, but device complexity increases
Solution Approach 1:
The formation of predetermined lines in the peripheral region is merged with the existing wafer fabrication process, eliminating the need for separate photolithography steps dedicated solely to alignment mark formation. This integration reduces process complexity while maintaining alignment precision.
Solution Approach 2:
The peripheral region serves multiple functions: it contains alignment marks for alignment, predetermined lines for position adjustment, and can accommodate other wafer handling features. This multi-functionality reduces the need for separate structures and processes, simplifying the overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables accurate alignment and lamination of device wafers without alignment marks, preserving the effective area for semiconductor devices and reducing manufacturing costs.
Implementation Method 1
a position adjusting step of imaging, by an imaging unit, a first predetermined line formed on a peripheral portion on the front surface side of the first device wafer and located outside the rectangular regions corresponding to the devices and a second predetermined line formed on a peripheral portion on the front surface side of the second device wafer and located outside the rectangular regions corresponding to the devices
Implementation Method 2
a thinning step of grinding and thinning a back surface side of the first device wafer after the removing step
Data Source
AI summary
A laminated device wafer forming method includes a laminating step of laminating a first device wafer and a second device wafer to each other, the laminating step including a position adjusting step of imaging, by an imaging unit, a first predetermined line formed on a peripheral portion on the front surface side of the first device wafer and located outside rectangular regions corresponding to devices and a second predetermined line formed on a peripheral portion on the front surface side of the second device wafer and located outside the rectangular regions corresponding to the devices, and adjusting relative positions of the first device wafer and the second device wafer by using the first predetermined line and the second predetermined line.