Wafer-Level Layout Pattern Density Mapping for Warping Prediction
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Solution Overview
Problem
Existing methods for analyzing layout pattern density in semiconductor manufacturing can only assess individual mask layers, failing to account for the superimposed impact of multiple layers and the impact on the wafer, which leads to nonuniform pattern density distribution and potential warping issues during the manufacturing process.
Innovation Solution
A method that involves merging chip layouts into a wafer-level layout, segmenting it into check windows, identifying and combining mask layers with height morphology, calculating pattern density, and creating a wafer-level pattern density distribution diagram that predicts the height morphology of the wafer surface, including the use of thin film thickness distribution to predict warping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If pattern density analysis is performed on only a single mask layer, then the analysis process is simple, but it cannot achieve analysis of superimposed impact of different mask layers and leads to nonuniform pattern density distribution
Solution Approach 1:
The patent merges multiple mask layers into a combined structure for simultaneous analysis. The system integrates pattern data from different mask layers and calculates their superimposed pattern density distribution together, enabling comprehensive analysis of the combined impact while maintaining computational efficiency through unified processing.
2Ease of manufacture
If existing single-layer pattern density analysis method is used, then the method is easy to implement, but it cannot predict wafer warping caused by complex layout patterns
Solution Approach 1:
The patent extends the analysis from two-dimensional single-layer pattern density to three-dimensional multi-layer superimposed pattern density distribution. By adding the vertical stacking dimension of multiple mask layers, the system can predict wafer warping more accurately while maintaining implementation feasibility through efficient computational methods.
3Manufacturing precision
If nonuniform pattern density distribution occurs, then etching loading effect is aggravated causing dimension deviation, but uniform distribution requires complex multi-layer analysis
Solution Approach 1:
The patent segments the wafer surface into multiple analysis regions and calculates pattern density distribution for each region considering superimposed mask layers. This segmentation approach enables precise identification of nonuniform density areas that cause etching loading effects, allowing targeted optimization while managing computational complexity through regional analysis.
Data Source
AI summary
The present application discloses a method for analyzing a layout pattern density, comprising: step 1, providing layouts of a chip, and merging the layouts to form a wafer level layout, wherein the wafer level layout presents a first circle in a top view, and the layout comprises a plurality of mask layers; step 2, segmenting the first circle to form a plurality of check windows; step 3, searching for the mask layer containing the patterns having a height morphology, and combining the found mask layers into a pattern layer combination; step 4, sequentially calculating a pattern density of the pattern layer combination in each check window; and step 5, recording the pattern density in each check window on a third circle to form a wafer level pattern density distribution diagram. The present application can predict a height morphology of a top surface of a wafer related to a layout.