Semiconductor Wafer Layout for Single Touch-Down Die Pair Testing

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Solution Overview

Problem

Conventional semiconductor test equipment requires two touch-downs to test all dies on a wafer due to the increasing number of dies exceeding the number of test heads, doubling the testing time and adding cost and inefficiencies.

Innovation Solution

The semiconductor wafer is configured with pairs of semiconductor dies electrically coupled through traces in the scribe lines, allowing for simultaneous testing of die pairs with a semiconductor test assembly in a single touch-down, using a probe card with test pins and power pins to differentiate and address each die pair.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional test equipment with fixed number of test heads is used, then the testing capability is limited by the number of test heads, but the number of dies on wafer has increased beyond the number of test heads

Engineering Contradiction:
Improvenumber of dies on waferVSAvoidtest equipment configuration
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The wafer is divided into multiple die pairs, where each pair shares common power and ground pads. This segmentation allows the test equipment to address pairs rather than individual dies, effectively reducing the number of test contacts needed while maintaining the ability to test all dies on the wafer.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The power and ground pads serve multiple functions: they provide power and ground for individual dies and simultaneously serve as shared resources for die pairs during testing. This multi-functionality reduces the total number of pads required compared to conventional individual die testing.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If two touch-downs are required to test all dies, then all dies can be tested, but the testing time is doubled

Engineering Contradiction:
Improvetesting completenessVSAvoidtesting time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Adjacent dies are merged into pairs that share common power and ground pads. This merging allows both dies in a pair to be tested simultaneously through a single touch-down of the probe card, eliminating the need for multiple touch-down operations and reducing total testing time.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single touch-down configuration allows continuous testing of all die pairs on the wafer without interruption or repositioning. The probe card maintains continuous contact with all test points during the testing process, eliminating the time loss associated with lifting and repositioning the probe card between touch-downs.

Inventive Principle:
Principle #20Continuity of useful action

3Reliability

If two touch-downs are required to test all dies, then all dies can be tested, but cost and inefficiencies are added

Engineering Contradiction:
Improvetesting completenessVSAvoidtesting efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By merging adjacent dies into pairs that share power and ground pads, the system reduces the number of test contacts required from the number of individual dies to half that number. This merging increases productivity by allowing all dies to be tested in a single touch-down operation, eliminating the inefficiencies of multiple touch-downs.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12270853B2Semiconductor wafer configured for single touch-down testing
Publication Date: 2025.04.08 SANDISK TECHNOLOGIES LLC
  • US12270853B2 patent drawing
  • US12270853B2 patent drawing
  • US12270853B2 patent drawing

AI summary

A semiconductor wafer includes pairs of semiconductor dies having test pads which are electrically coupled to each other to enable testing of pairs of semiconductor dies together at the same time. In this way, even wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process.