Semiconductor Wafer Layout for Fewer Lithography Shots
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Solution Overview
Problem
Current semiconductor wafer fabrication techniques require multiple lithography shots due to uniform chip region sizes, leading to reduced productivity and increased processing time.
Innovation Solution
The semiconductor wafer design incorporates unit regions with first and second chip regions of different area sizes, arranged in a lattice pattern with scribe lines, allowing for efficient use of space and minimizing the number of shots required during the lithography process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If uniform chip region sizes are used in semiconductor wafer fabrication, then manufacturing simplicity is maintained, but the number of lithography shots increases reducing productivity
Solution Approach 1:
The patent applies asymmetry by intentionally designing chip regions with different area sizes within the same wafer. Specifically, first chip regions and second chip regions have different dimensions, allowing more chip regions to be accommodated per lithography shot. This asymmetric design optimizes space utilization and reduces the total number of shots required, directly improving productivity while accepting increased design complexity.
Solution Approach 2:
The patent implements local quality by assigning different characteristics to different regions of the wafer. Different chip regions are designed with different area sizes based on their specific functional requirements and density needs. This allows high-density regions to be packed more efficiently while low-density regions maintain adequate spacing, optimizing overall wafer utilization and reducing the number of lithography shots needed.
2Productivity
If multiple lithography shots are used, then complete chip patterns are formed, but processing time increases reducing productivity
Solution Approach 1:
The patent applies merging by combining multiple different-sized chip regions into a single lithography shot. By carefully arranging first chip regions and second chip regions with different area sizes within one shot area, the patent reduces the total number of shots required. This merging approach maintains complete chip patterns while significantly reducing processing time and improving productivity.
3Productivity
If chip regions are spaced apart by scribe lines, then chip separation is enabled, but space utilization decreases increasing the number of shots
Solution Approach 1:
The patent applies preliminary action by pre-planning and optimizing the arrangement of chip regions with different area sizes before fabrication. The scribe lines are strategically positioned to minimize wasted space while ensuring chip separation capability. This preliminary optimization of layout allows maximum space utilization within each lithography shot, reducing the total number of shots needed while maintaining ease of chip separation during dicing.
Data Source
AI summary
A semiconductor wafer includes unit regions that are repeatedly arranged, and each unit region of the unit regions includes: at least one first chip region; and at least one second chip region spaced apart from the at least one first chip region by a scribe line, wherein a first area size of each of the at least one first chip region is different from a second area size of each of the at least one second chip region from a planar viewpoint.