Wafer Layout Inspection for Bonding Pad Step Difference Control
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Solution Overview
Problem
In the wafer-to-wafer bonding process for manufacturing multichip packages, existing methods face challenges in ensuring that bonding pads and insulating layers have a step difference within a predetermined range, which affects proper bonding and electrical characteristics.
Innovation Solution
A method involving the formation of a test pattern with metal lines on the wafer surface, using atomic force microscopy (AFM) to measure surface roughness and determine step differences, and adjusting the CMP process to ensure bonding pads and insulating layers have a step difference within a target range, thereby improving bonding quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If bonding pads protrude beyond a predetermined height compared to the insulating layer, then bonding pad visibility and accessibility improve, but proper bonding between insulating layers becomes difficult
Solution Approach 1:
The patent applies parameter changes by precisely controlling the height parameter of bonding pads relative to the insulating layer. Through the CMP process, the bonding pads are polished to achieve a specific height range that allows both accessibility and proper bonding, transforming the dimensional parameter to resolve the contradiction between protrusion benefits and bonding quality requirements.
2Reliability
If bonding pads are recessed beyond a predetermined depth compared to the insulating layer, then bonding pad protection improves, but electrical characteristics between bonding pads deteriorate
Solution Approach 1:
The patent controls the depth parameter of recessed bonding pads within a specific range using the CMP process. By adjusting the polishing parameters and duration, the bonding pads are recessed enough to be protected by the insulating layer while maintaining sufficient exposure to preserve electrical characteristics, thus resolving the contradiction between protection and electrical performance.
3Ease of operation
If manual inspection methods are used to monitor step difference, then measurement flexibility improves, but automation and efficiency deteriorate
Solution Approach 1:
The patent replaces manual mechanical inspection with an automated optical measurement system. The system uses optical microscopy or interferometry to automatically capture images of the wafer surface and calculate step differences between bonding pads and the insulating layer, eliminating manual measurement while maintaining measurement capability and enabling high-throughput automated inspection.
4Device complexity
If no test pattern is used for monitoring, then process complexity reduces, but automated monitoring capability is lost
Solution Approach 1:
The patent introduces a test pattern as an intermediary element that facilitates automated monitoring. The test pattern consists of reference structures with known dimensions that serve as calibration markers and measurement references. By incorporating these intermediate reference structures into the wafer design, the system can automatically calculate step differences without adding significant process complexity, enabling automated quality control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables automated monitoring and adjustment of step differences, enhancing the yield and quality of multichip packages by ensuring accurate bonding and electrical connectivity between wafers.
Implementation Method 1
determining a surface roughness value of the test region by measuring the test region in which the metal lines are formed using an atomic force microscope (AFM)
Implementation Method 2
polishing the metal layer using a chemical mechanical polishing (CMP) process such that bonding pads and metal lines are formed based on the bonding pad pattern and the line pattern, respectively
Data Source
AI summary
In a manufacturing method of a wafer, the method including: an operation of preparing a wafer including a semiconductor chip region and a test region, measuring a measurement region included in the test region with an atomic force microscope (AFM), the measurement region including a plurality of metal lines having a constant line width and a constant pitch; determining a surface roughness value of the test region based on a result of the measuring of the measurement region; determining a step difference value of the metal lines of the test region based on the surface roughness value; and determining a step difference value of bonding pads in the semiconductor chip region based on the step difference value of the metal lines.