Wafer Layout Design Optimizing Yield Edge Position
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Solution Overview
Problem
The yield of qualified dies on semiconductor wafers is often lower than calculated due to process control limitations, particularly near the wafer edge, resulting in incomplete or damaged dies during the production of initial wafer layouts.
Innovation Solution
A design method for wafer layout that includes creating a yield distribution map, determining the yield edge position, and recalculating the layout based on die size and this edge position to optimize the number of qualified dies, with an exposure system using a processor and memory to execute and implement the new layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the wafer layout is calculated according to die size and wafer edge cleaning position to maximize the number of complete dies, then the number of complete dies per wafer is increased, but the yield of qualified dies decreases due to process control issues near the wafer edge
Solution Approach 1:
The patent applies local quality by differentiating the treatment of different regions on the wafer. The wafer is divided into a first area (center region) and a second area (edge region), with different yield characteristics. The layout calculation specifically considers the lower yield in the second area by adjusting the effective wafer radius to the yield edge position, thereby optimizing the distribution of dies to account for regional quality differences and improve overall qualified die yield.
2Productivity
If the wafer layout includes dies near the wafer edge to increase production capacity, then the number of dies per wafer is increased, but the number of damaged or incomplete dies increases due to poor process control at the edge
Solution Approach 1:
The patent changes the parameter of wafer radius from the physical edge to the yield edge position (an internal radius where yield drops to zero or a threshold). This parameter transformation allows the layout to exclude the low-yield edge region while maximizing the use of the high-yield central region, thereby maintaining manufacturing precision without sacrificing unnecessary production capacity.
3Device complexity
If the initial wafer layout is used without considering yield distribution, then the layout calculation is simple and fast, but the actual number of qualified dies obtained is less than calculated
Solution Approach 1:
The patent applies preliminary action by pre-establishing the yield distribution map and determining the yield edge position before performing the layout calculation. This preliminary analysis of yield characteristics allows the subsequent layout optimization to be more accurate, ensuring that the calculated number of qualified dies closely matches the actual obtained number, thereby improving prediction accuracy without excessive complexity.
Data Source
AI summary
Embodiments of the present application relate to the technical field of semiconductor, and disclose a design method of a wafer layout and an exposure system of a lithography machine. The design method of a wafer layout includes: providing a yield distribution map of a wafer under an initial wafer layout; determining a yield edge position of the wafer according to the yield distribution map; and calculating a new wafer layout according to a die size and the yield edge position.