Wafer-Level LED Structure Early Inspection Yield
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Solution Overview
Problem
Conventional thin film light emitting diode (TF-LED) manufacturing processes face challenges in measuring photoelectric properties during the fabrication phase, leading to a poor yield rate of 50% or worse, as semiconductor processes are performed after bonding with a support substrate, making it difficult to identify and discard flawed chips early on.
Innovation Solution
A wafer-level light emitting diode structure with a substrate and semiconductor layers, including extended and protruded portions, allows for the placement of electrodes for early inspection of photoelectric properties, enabling identification and categorization of chips that meet predetermined standards before further processing, thereby increasing yield and reducing waste.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor processes are performed after bonding with support substrate, then complete LED structure is formed, but photoelectric properties cannot be inspected early leading to poor yield rate
Solution Approach 1:
The patent segments the LED structure into two functional zones: a stacked structure region containing the light emitting diode (semiconductor layers with light emitting layer) and a non-stacked structure region containing extended portions of semiconductor layers. This segmentation allows the first electrode to be formed on the extended portion, enabling early photoelectric inspection before bonding to support substrate, thus improving yield rate without complicating the overall process sequence.
Solution Approach 2:
The patent extends the first semiconductor layer in the horizontal dimension beyond the stacked structure region, creating an extended portion that protrudes from the stacked structure. This dimensional extension provides a dedicated area for forming the first electrode and conducting photoelectric inspections before bonding, allowing early detection of flawed chips and improving yield rate.
2Loss of substance
If all chips undergo bonding and subsequent fabrication processes, then complete LED chips are produced, but flawed chips cannot be identified early causing material waste
Solution Approach 1:
The patent performs preliminary photoelectric property inspection on the epi wafer before bonding to support substrate by forming the first electrode on the extended portion of the first semiconductor layer. This preliminary action enables identification and discarding of flawed chips early in the manufacturing process, preventing material waste from processing defective chips through subsequent bonding and fabrication steps.
Solution Approach 2:
The patent extracts the inspection function from the post-bonding process by creating an extended portion of the first semiconductor layer that protrudes from the stacked structure. This extracted region allows formation of the first electrode and conductive to photoelectric inspection before bonding, enabling early identification and removal of flawed chips, thus reducing material waste.
3Measurement precision
If first electrode is formed on extended portion overlapping cutting range, then photoelectric inspection is enabled before bonding, but cutting process becomes more complex
Solution Approach 1:
The patent applies local quality by creating an extended portion of the first semiconductor layer with specific spatial characteristics - it extends from the stacked structure and overlaps with the cutting range. This localized structural modification enables the first electrode to be formed in a specific region for photoelectric inspection, while the cutting process can still proceed by removing the extended portion, thus enabling measurement without significantly complicating the cutting process.
Data Source
AI summary
A method for fabricating a wafer-level light emitting diode structure is provided. The method includes: providing a substrate, wherein a first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially disposed on the substrate; subjecting the first semiconductor layer, the light emitting layer, and the second semiconductor layer with a patterning process to form a first depressed portion, a second depressed portion, a stacked structure disposed on the second depressed portion and a remained first semiconductor layer disposed on the depressed portion, wherein the stacked structure comprises a patterned second semiconductor layer, a patterned emitting layer, and a patterned first semiconductor layer; forming a first electrode on the remained first semiconductor layer of the first depressed portion; and forming a second electrode correspondingly disposed on the patterned second semiconductor layer of the second depressed portion.